Abstract: A multi-step analog-to-digital converter (ADC). The ADC includes a sampling circuitry, a comparator, a trimming circuitry, and a DC offset actuator. The sampling circuitry is configured to sample an input analog signal. The comparator is for comparing the input analog signal sample or a residual component of the input analog signal sample to a reference value in each step. The trimming circuitry is configured to receive at least one low-order bit (e.g., a least significant bit and/or a second-least significant bit) of digital binary bits of each input analog signal sample and average the low order bit over a plurality of input analog signal samples and generate a control signal for correcting an input DC offset of the comparator based on an average value of the low-order bits. The DC offset actuator is configured to correct the input DC offset of the comparator based on the control signal.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of differential capacitive digital-to-analog converters (C-DACs), comparators, and an SAR controller. Each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array. A capacitor for each bit position may include a pair of equal-sized capacitors. Each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs. The SAR controller generates a control signal for the differential C-DACs for each conversion step based on outputs of the comparators. The outputs of the comparators are provided to the differential C-DACs as the control signal without encoding. Single-bit/cycle shorting switches for shorting top plates of capacitors of the C-DACs of same polarity may be closed during a single-bit/cycle conversion.