Abstract: Apparatuses, systems, and techniques to facilitate parallel processing. In at least one embodiment, an application programming interface allows a user to define a plurality of cooperative thread groups, and launch multiple cooperative thread groups in parallel provided sufficient processing resources are available.

Abstract: Apparatuses, systems, and techniques to implement a barrier operation. In at least one embodiment, a memory barrier operation causes accesses to memory by a plurality of groups of threads to occur in an order indicated by the memory barrier operation.

Abstract: Apparatuses, systems, and techniques to control operation of a memory cache. In at least one embodiment, cache guidance is specified within application source code by associating guidance with declaration of a memory block, and then applying specified guidance to source code statements that access said memory block.

Abstract: Apparatuses, systems, and techniques to parallelize operations in one or more programs with data copies from global memory to shared memory in each of the one or more programs. In at least one embodiment, a program performs operations on shared data and then asynchronously copies shared data to shared memory, and continues performing additional operations in parallel while the shared data is copied to shared memory until an indicator provided by an application programming interface to facilitate parallel computing, such as CUDA, informs said program that shared data has been copied to shared memory.

Abstract: Apparatuses, systems, and techniques to parallelize operations in one or more programs with data copies from global memory to shared memory in each of the one or more programs. In at least one embodiment, a program performs operations on shared data and then asynchronously copies shared data to shared memory, and continues performing additional operations in parallel while the shared data is copied to shared memory until an indicator provided by an application programming interface to facilitate parallel computing, such as CUDA, informs said program that shared data has been copied to shared memory.

Abstract: Apparatuses, systems, and techniques to parallelize operations in one or more programs with data copies from global memory to shared memory in each of the one or more programs. In at least one embodiment, a program performs operations on shared data and then asynchronously copies shared data to shared memory, and continues performing additional operations in parallel while the shared data is copied to shared memory until an indicator provided by an application programming interface to facilitate parallel computing, such as CUDA, informs said program that shared data has been copied to shared memory.

Abstract: Apparatuses, systems, and techniques to execute data-dependent parallel operations in one or more programs utilizing an application programming interface to perform parallel computing, such as CUDA, without relying on a synchronization operation between said one or more programs. For example, at least one embodiment pertains to processors or computing systems used to determine which thread in a group of threads finishes modifying shared data last, and that thread is selected to perform additional data-dependent computations from said group of threads.

Abstract: Apparatuses, systems, and techniques to perform multi-threaded memory allocation in parallel by one or more software programs being performed on a parallel processing unit (PPU), such as a graphics processing unit (GPU), or any other processing unit capable of supporting multi-threaded software execution. In at least one embodiment, one or more software programs expressed in part by code using an application programming interface for parallel computing, such as CUDA, perform allocation, search, and deallocation of memory efficiently and in parallel on a GPU.

Abstract: An application for a pre-configured Internet protection device includes a processor with a first network interface for connecting to a World-Wide-Web or other external network coupled to the processor and a second network interface for connecting to at least one terminal device also coupled to the processor. Software for preventing access from the terminal device to at least one web service executes on the processor, whereas the software is pre-configured with lists, algorithms, processes and methods for protecting a pre-determined class of user.

Abstract: The present invention relates to the discovery that signaling via a serotonin type 1B, 2, 4 and 6 receptor is important in T cell activation such that inhibiting such signaling can be used to modulate the immune response. This immunomodulation is useful for the treatment of immune diseases or conditions, and for the development of potential therapeutics for such diseases or conditions. It has been further discovered that, in cells proceeding through the cell cycle process, inhibition of serotonin signaling inhibits the process and induces apoptosis and morphological changes to a cell. These effects of inhibiting serotonergic signaling can be useful for effecting selective cell killing and for identifying compounds that inhibit the signaling.

Abstract: The present invention relates to the discovery that signaling via a serotonin type 1B, 2, 4 and 6 receptor is important in T cell activation such that inhibiting such signaling can be used to modulate the immune response. This immunomodulation is useful for the treatment of immune diseases or conditions, and for the development of potential therapeutics for such diseases or conditions. It has been further discovered that, in cells proceeding through the cell cycle process, inhibition of serotonin signaling inhibits the process and induces apoptosis and morphological changes to a cell. These effects of inhibiting serotonergic signaling can be useful for effecting selective cell killing and for identifying compounds that inhibit the signaling.