Abstract: A method, system, computer system, and computer-readable medium to efficiently coordinate caching operations between nodes operating on the same file while allowing different regions of the file to be written concurrently. More than one program can concurrently read and write to the same file. Pages of data from the file are proactively and selectively cached and flushed on different nodes. In one embodiment, range locks are used to effectively flush and invalidate only those pages that are accessed on another node.

Abstract: A method, system, application programming interface, computer system, and computer program product to provide locks for controlling access to data by nodes in a multi-node environment while minimizing messages sent between nodes. Based upon knowledge of lock usage in the multi-node environment, a multi-node knowledge agent can determine when no other node is accessing data protected by a given lock, as well as when an event has occurred that precedes a request by another node to access data protected by the given lock. When no other node is accessing data and no such event has occurred, the multi-node knowledge agent can designate that given lock as “masterless.” A lock agent on the node hosting the multi-node knowledge agent is authorized to subsequently grant access to the data protected by the masterless lock to clients on that node without communicating with a lock master, which may reside at another node.

Abstract: The present invention advantageously optimizes the flexibility built into some interleavers by novelly configuring an interleaver to improve the throughput of access to computer memory by maximizing the number of banks used for interleaving the memory. That is, the present embodiment improves the process of spreading memory references across multiple memory banks to increase throughput of the memory system by novelly configuring the control registers of an interleaver in a computer system. The present invention configures an interleaver so that it operates across “N” memory banks where “N” is not required to be a power of two. That is, the current embodiment of the present invention may approximate the number of memory banks available for interleaving to the a number that is equal to or closer to the number of memory banks available for interleaving, than previous solutions that were constrained to a power of two.