Patents by Inventor Harold Carter Edwards

Harold Carter Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STORAGE OF TRANSFORMED TENSOR IN A CACHE
    Publication number: 20240169472
    Abstract: Apparatuses, systems, and techniques to perform a tensor prefetch instruction to cause one or more tensors to be transformed and stored into one or more caches. In at least one embodiment, one or more circuits of a GPU are to perform a tensor prefetch instruction to cause one or more tensors to be transformed and stored into one or more GPU caches.
    Type: Application
    Filed: December 21, 2022
    Publication date: May 23, 2024
    Inventors: Harold Carter Edwards, Stephen Anthony Bernard Jones, Alexander Lev Minkin, Olivier Giroux, Gokul Ramaswamy Hirisave Chandra Shekhara, Aditya Avinash Atluri, Apoorv Parle, Ronny Meir Krashinsky, Alan Kaatz, Andrew Robert Kerr, Jack H. Choquette
  • APPLICATION PROGRAMMING INTERFACE TO GENERATE A TENSOR ACCORDING TO A TENSOR MAP
    Publication number: 20240161224
    Abstract: Apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map without storing information about a memory transaction corresponding to the translation. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a first tensor to be translated into a second tensor according to a tensor map without storing information about one or more memory transactions corresponding to the translation.
    Type: Application
    Filed: December 21, 2022
    Publication date: May 16, 2024
    Inventors: Harold Carter Edwards, Stephen Anthony Bernard Jones, Alexander Lev Minkin, Olivier Giroux, Gokul Ramaswamy Hirisave Chandra Shekhara, Vishalkumar Ketankumar Mehta, Aditya Avinash Atluri, Apoorv Parle, Chao Li, Ronny Meir Krashinsky, Alan Kaatz, Andrew Robert Kerr, Jack H. Choquette
  • APPLICATION PROGRAMMING INTERFACE TO INDICATE IMAGE-TO-COLUMN TRANSFORMATION
    Publication number: 20240161222
    Abstract: Apparatuses, systems, and techniques to indicate how to generate image-to-column transformations. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to indicate how to generate one or more image-to-column transformations.
    Type: Application
    Filed: December 21, 2022
    Publication date: May 16, 2024
    Inventors: Harold Carter Edwards, Stephen Anthony Bernard Jones, Alexander Lev Minkin, Olivier Giroux, Gokul Ramaswamy Hirisave Chandra Shekhara, Vishalkumar Ketankumar Mehta, Aditya Avinash Atluri, Apoorv Parle, Ronny Meir Krashinsky, Alan Kaatz, Andrew Robert Kerr, Jack H. Choquette
  • APPLICATION PROGRAMMING INTERFACE TO TRANSLATE A TENSOR
    Publication number: 20240161223
    Abstract: Apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a first tensor to be translated into a second tensor according to a tensor map.
    Type: Application
    Filed: December 21, 2022
    Publication date: May 16, 2024
    Inventors: Harold Carter Edwards, Stephen Anthony Bernard Jones, Alexander Lev Minkin, Olivier Giroux, Gokul Ramaswamy Hirisave Chandra Shekhara, Vishalkumar Ketankumar Mehta, Aditya Avinash Atluri, Apoorv Parle, Chao Li, Ronny Meir Krashinsky, Alan Kaatz, Andrew Robert Kerr, Jack H. Choquette
  • APPLICATION PROGRAMMING INTERFACE TO SCHEDULE THREAD BLOCKS
    Publication number: 20240036952
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to determine which of two or more blocks of threads are to be scheduled in parallel.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO INDICATE PARALLEL SCHEDULING MAXIMUM
    Publication number: 20240036916
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a maximum number of blocks of threads capable of being scheduled in parallel.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO INDICATE ATTRIBUTE LIMITATIONS
    Publication number: 20240036955
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO INDICATE PERFORMANCE OF BARRIER INSTRUCTION AND STOP PERFORMANCE OF THREADS
    Publication number: 20240036956
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate whether one or more threads within a group of blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO PERFORM A SCHEDULING POLICY
    Publication number: 20240036915
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to determine a scheduling policy of one or more blocks of one or more threads.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO INDICATE SCHEDULING POLICIES
    Publication number: 20240036953
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a scheduling policy of one or more blocks of one or more threads.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO INDICATE BLOCK MAXIMUM
    Publication number: 20240036917
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a maximum number of blocks of threads to be scheduled in parallel.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO GENERATE KERNELS
    Publication number: 20240036918
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO INDICATE PERFORMANCE OF BARRIER INSTRUCTION
    Publication number: 20240036944
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO STOP PERFORMANCE OF THREADS
    Publication number: 20240036945
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO INDICATE ATTRIBUTES OF GROUPS OF BLOCKS OF THREADS
    Publication number: 20240036954
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more attributes of one or more groups of blocks of one or more threads.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO INDICATE THREAD BLOCKS
    Publication number: 20240036951
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate two or more blocks of threads to be scheduled in parallel.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • APPLICATION PROGRAMMING INTERFACE TO SHARE MEMORY BETWEEN GROUPS OF BLOCKS OF THREADS
    Publication number: 20240036957
    Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause memory to be shared between two or more groups of blocks of threads.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 1, 2024
    Inventors: Ze Long, Kyrylo Perelygin, Harold Carter Edwards, Gokul Ramaswamy Hirisave Chandra Shekhara, Jaydeep Marathe, Ronny Meir Krashinsky, Girish Bhaskarrao Bharambe
  • TECHNIQUES TO SELECTIVELY STORE DATA
    Publication number: 20230305845
    Abstract: Apparatuses, systems, and techniques to cause data to be selectively stored in one or more memory locations. In at least one embodiment, a processor is to cause data to be selectively stored in one or more memory locations based, at least in part, on one or more threads to use the data.
    Type: Application
    Filed: March 31, 2022
    Publication date: September 28, 2023
    Inventors: Harold Carter Edwards, Stephen Anthony Bernard Jones, David Anthony Fontaine, Sebastian Piotr Jodlowski, Aditya Avinash Atluri, Andrew Robert Kerr, Michael Andrew Clark, Gonzalo Brito Gadeschi, Olivier Giroux, Jaydeep Marathe, Thibaut Lutz, Hariharan Sandanagobalane, Gokul Ramaswamy Hirisave Chandra Shekhara, Girish Bhaskarrao Bharambe, Rishkul Kulkarni, Konstantinos Kyriakopoulos
  • APPLICATION PROGRAMMING INTERFACE TO PERFORM OPERATION WITH REUSABLE THREAD
    Publication number: 20230305853
    Abstract: Apparatuses, systems, and techniques to perform collective operations using parallel processing. In at least one embodiment, a non-blocking application programming interface allow programs to improve performance of one or more collective operations on a GPU.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Inventors: Piotr Ciolkosz, Kyrylo Perelygin, Harold Carter Edwards, Wesley Maxey
  • APPLICATION PROGRAMMING INTERFACE FOR SCAN OPERATIONS
    Publication number: 20230111125
    Abstract: Apparatuses, systems, and techniques to perform parallel processing. In at least one embodiment, a parallel processing algorithm for performing an additive prefix scan is selected from a plurality of alternatives based on an arrangement of a group of threads provided to perform the scan.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 13, 2023
    Inventors: Piotr Ciolkosz, Kyrylo Perelygin, Harold Carter Edwards, Wesley Maxey