Abstract: A method and system comprising a host system and a host bus adapter (HBA). The HBA is configured to handle a Virtual Interface and Transmission Control Protocol (TCP)/Internet Protocol (IP) processing for applications running on the host system.

Abstract: The avoidance of port collisions in a hardware-accelerated network protocol, such as Transmission Control Protocol (TCP)/Internet Protocol (IP), is disclosed. In one example, a hardware-accelerated host bus adaptor (HBA) offloads protocol processing from a host computer's operating system. However, a port collision occurs if a non-accelerated host TCP/IP stack and a hardware accelerated host bus adapter TCP/IP stack choose the same port for establishing a network connection. In a double-ended TCP/IP acceleration connection, a unique TCP port is bound to the accelerated TCP/IP stack. In a single-ended TCP/IP acceleration connection, either the host TCP/IP stack is prevented from using that port or a non-accelerated connection is associated with an accelerated connection without binding a port.

Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.

Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.

Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.

Abstract: A clock security ring provides improved clock system error detection and (a.c.) fault isolation. The clock security ring is formed by a plurality of fault detection circuits and a plurality of error collection circuits each receiving inputs from respective subsets of the plurality of fault detection circuits. The error collection circuits comprise a logical network which provides a detected fault output for any fault pattern which leaves at least one fault detection circuit in a predefined correct state. Each of the subsets of fault detection circuits has an arbitrary grouping of fault detection circuits plus one fault detection circuit from an adjacent subset to thereby form a ring structure. The outputs of the error collection circuits are analyzed to provide fault isolation.