Abstract: A method for constructing a semiconductor-on-insulator is provided. A sacrificial layer (12) of a predetermined thickness is first formed on a semiconductor wafer (10) surface. The wafer (10) is then subjected to an ion implantation process to place the ions (16) at predetermined depths below the semiconductor wafer surface. During the implantation process, the sacrificial layer (12) is gradually sputtered away and thereby compensating the gradual outgrowth of the silicon surface due to the volume of the implanted ions (16). A post-implant anneal is performed to allow the ions (16) to react with the semiconductor to form a buried insulating layer (24).

Abstract: A resonant tunneling diode (400) made of a silicon quantum well (406) with silicon oxide tunneling barriers (404, 408). The tunneling barriers have characteristics of implanted oxygen segregated into oxide layers.

Abstract: An infrared or x-ray imaging CCD array, including deep trench isolation (56) for capturing electron carriers formed deep in the substrate (46) as a result of long wavelength radiation or high energy particles. In virtual phase CCD circuits, the trench has formed on the sidewalls thereof a diffusion (58, 60) defining a vertical conductor for allowing hole carrier conduction between the substrate (46) and the virtual phase electrode (38).

Abstract: An infrared or x-ray imaging CCD array, including deep trench isolation (56) for capturing electron carriers formed deep in the substrate (46) as a result of long wavelength radiation or high energy particles. In virtual phase CCD circuits, the trench has formed on the sidewalls thereof a diffusion (58, 60) defining a vertical conductor for allowing hole carrier conduction between the substrate (46) and the virtual phase electrode (38).

Abstract: A CCD imager array is formed at a face (30) of a semiconductor layer (12) and comprises a plurality of CCD cells (34) formed in rows and columns. A plurality of continuous buried gates (27) are each disposed between adjacent columns of the cells (34), and each buried gate (27) extends from the face (30) into the semiconductor layer (12). Each buried gate (27) includes a gate conductor (24) and a gate insulator (26). The buried gates (27) define for each cell (34) a charge collection region (66). A bias voltage source is operable to selectively apply a bias voltage (60) to the buried gate conductors (24), thereby creating a depletion region (64) that substantially includes the charge collection region (66). CCD clock gates (32) are operated independently of the buried gates (27) to read out the charge collected during an integration phase (58). The array of the invention is particularly useful in recording X-ray and near infrared electromagnetic radiation.

Abstract: A parallel readout stratified channel CCD includes a plurality of parallel spaced apart charge transfer channels lying in a semiconductor substrate. A barrier region lies under and adjacent to all the charge transfer channels and their separating regions. A charge integration channel lies under and adjacent to the barrier region. The substrate and barrier region have dopant of atoms of a first type; while a charge integration channel has dopant of atoms of a second type opposite to the first type. An insulating layer overlies the charge transfer channel, and a plurality of phase electrodes are serially disposed thereon transversely to all of the charge transfer channels. Further included are interchannel transfer regions under selected portions of predetermined ones of the electrodes. These enable localized interchannel charge transfer.

Abstract: An improved method and structure for producing narrow openings to the surface of a first material possessing a first set of etch characteristics is disclosed. The method includes the step of forming on a portion of the surface of the first material an etchable mask having a first narrow-opening-forming lateral edge disposed along a selected edge of the to-be-formed narrow opening. A protective layer of a second material possessing a second set of etch characteristics is next formed on the exposed surface of the first material, the protective layer having a second narrow-opening-forming lateral edge juxtaposed the first narrow-opening-forming lateral edge. The first narrow-opening-forming lateral edge on the mask is then etched to expose unprotected areas of the first material thereby producing the narrow opening to the surface of the first material. The method and structure of the invention is particularly well suited for producing fine geometry patterns in solid state device structures.

Abstract: An improved method for producing a plurality of closely-spaced altered regions in the surface of a first material possessing a first set of etch characteristics is disclosed. The method includes the steps of forming an etchable mask of a second material over a portion of the first material, which mask has a second set of etch characteristics and a lateral edge disposed along a selected edge of a first of the to-be-altered closely-spaced regions in the first material. A protective layer of a third material possessing a third set of etch characteristics is next formed on the exposed surface of the first material, the protective layer having a second lateral edge juxtaposed the first lateral edge. The first lateral edge of the mask is then etched to expose unprotected portions of the first material. The exposed unprotected portions of the first material are then altered by either etching or diffusion.