Abstract: A method is provided to assign component I/O (input/output, the interface area between levels of physical packaging) pins for all components at each level of the computer system. In a hierarchical, top-down design methodology, the I/O pins for each computer system component are assigned to nets (a net is an interconnection of pins on a level of packaging, or between levels of packaging) based on wire length, electrical limits and timing. Parameters that are considered are net priority (the importance of this net to the system, relative to other nets in the system), location of physical components, location of physical component I/Os at all computer system levels of physical packaging hierarchy, and I/O pin characteristics. An iterative method is used to assign and reassign I/O pins at each level based on timing. As I/Os are reassigned at each lower component level, new assignments are made at all higher levels of the system packaging hierarchy based on the changed parameters at the lower level.

Abstract: A high speed digital multiplier utilizes a variation in known shift-and-add algorithms. Each cycle, a single digit of the multiplier and the entire multiplicand are processed to form a "partial product" that is added to the result of the next cycle. The end result is a two part product, the high order product being generated by a carry-propagate adder, and the low order product being generated by a "spill adder" that produces one digit each cycle. Inputs of a carry-propagate adder are fed directly from outputs of a carry-save adder rather than running sum and carry registers. With a multiplier digit of 16-bits, a fixed point halfword multiply requires one execution cycle, a fixed point fullword multiply requires two execution cycles, and a floating point long multiply requires four execution cycles with additional overhead if pre- or post-normalization is required.