Patents by Inventor Harold Kennel
Harold Kennel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145549Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventors: Siddharth CHOUKSEY, Glenn GLASS, Anand MURTHY, Harold KENNEL, Jack T. KAVALIEROS, Tahir GHANI, Ashish AGRAWAL, Seung Hoon SUNG
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Patent number: 11973143Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.Type: GrantFiled: March 28, 2019Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Ryan Keech, Benjamin Chu-Kung, Subrina Rafique, Devin Merrill, Ashish Agrawal, Harold Kennel, Yang Cao, Dipanjan Basu, Jessica Torres, Anand Murthy
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Patent number: 11929435Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.Type: GrantFiled: August 30, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Harold Kennel, Tahir Ghani
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Patent number: 11923421Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.Type: GrantFiled: July 20, 2022Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Siddharth Chouksey, Glenn Glass, Anand Murthy, Harold Kennel, Jack T. Kavalieros, Tahir Ghani, Ashish Agrawal, Seung Hoon Sung
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Publication number: 20240006489Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.Type: ApplicationFiled: September 13, 2023Publication date: January 4, 2024Inventors: Aaron LILAK, Rishabh MEHANDRU, Willy RACHMADY, Harold KENNEL, Tahir GHANI
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Patent number: 11798991Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.Type: GrantFiled: June 28, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Aaron Lilak, Rishabh Mehandru, Willy Rachmady, Harold Kennel, Tahir Ghani
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Patent number: 11756998Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.Type: GrantFiled: January 14, 2022Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Cheng-Ying Huang, Tahir Ghani, Jack Kavalieros, Anand Murthy, Harold Kennel, Gilbert Dewey, Matthew Metz, Willy Rachmady, Sean Ma, Nicholas Minutillo
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Patent number: 11695081Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.Type: GrantFiled: June 29, 2018Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Sean Ma, Nicholas Minutillo, Cheng-Ying Huang, Tahir Ghani, Jack Kavalieros, Anand Murthy, Harold Kennel, Gilbert Dewey, Matthew Metz, Willy Rachmady
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Patent number: 11637185Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.Type: GrantFiled: September 25, 2018Date of Patent: April 25, 2023Assignee: Intel CorporationInventors: Justin Weber, Harold Kennel, Abhishek Sharma, Christopher Jezewski, Matthew V. Metz, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Van H. Le, Arnab Sen Gupta
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Publication number: 20230006065Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.Type: ApplicationFiled: August 30, 2022Publication date: January 5, 2023Applicant: Intel CorporationInventors: Gilbert DEWEY, Willy RACHMADY, Jack T. KAVALIEROS, Cheng-Ying HUANG, Matthew V. METZ, Sean T. MA, Harold KENNEL, Tahir GHANI
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Publication number: 20220416032Abstract: Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Debaleena Nandi, Chi-Hing Choi, Gilbert Dewey, Harold Kennel, Omair Saadat, Jitendra Kumar Jha, Adedapo Oni, Nazila Haratipour, Anand Murthy, Tahir Ghani
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Publication number: 20220406895Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.Type: ApplicationFiled: July 20, 2022Publication date: December 22, 2022Inventors: Siddharth CHOUKSEY, Glenn GLASS, Anand MURTHY, Harold KENNEL, Jack T. KAVALIEROS, Tahir GHANI, Ashish AGRAWAL, Seung Hoon SUNG
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Patent number: 11515420Abstract: An apparatus is provided which comprises: a first region over a substrate, wherein the first region comprises a first semiconductor material having a L-valley transport energy band structure, a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction, and a metal adjacent to the second region, the metal conductively coupled to the first region through the junction. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 29, 2017Date of Patent: November 29, 2022Assignee: INTEL CORPORATIONInventors: Dax M. Crum, Cory E. Weber, Rishabh Mehandru, Harold Kennel, Benjamin Chu-Kung
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Patent number: 11508577Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.Type: GrantFiled: June 29, 2018Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Gilbert Dewey, Matthew Metz, Willy Rachmady, Sean Ma, Nicholas Minutillo, Cheng-Ying Huang, Tahir Ghani, Jack Kavalieros, Anand Murthy, Harold Kennel
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Patent number: 11469323Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.Type: GrantFiled: September 25, 2018Date of Patent: October 11, 2022Assignee: Intel CorporationInventors: Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Harold Kennel, Tahir Ghani
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Patent number: 11462568Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.Type: GrantFiled: June 22, 2018Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Aaron Lilak, Justin Weber, Harold Kennel, Willy Rachmady, Gilbert Dewey, Van H. Le, Abhishek Sharma, Patrick Morrow, Ashish Agrawal
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Patent number: 11437472Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.Type: GrantFiled: June 28, 2018Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Siddharth Chouksey, Glenn Glass, Anand Murthy, Harold Kennel, Jack T. Kavalieros, Tahir Ghani, Ashish Agrawal, Seung Hoon Sung
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Publication number: 20220199402Abstract: High-purity Ge channeled N-type transistors include a Si-based barrier material separating the channel from a Ge source and drain that is heavily doped with an N-type impurity. The barrier material may have nanometer thickness and may also be doped with N-type impurities. Because of the Si content, N-type impurities have lower diffusivity within the barrier material and can be prevented from entering high-purity Ge channel material. In addition to Si, a barrier material may also include C. With the barrier material, an N-type transistor may display higher channel mobility and reduced short-channel effects.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Koustav Ganguly, Ryan Keech, Harold Kennel, Willy Rachmady, Ashish Agrawal, Glenn Glass, Anand Murthy, Jack Kavalieros
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Patent number: 11367789Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.Type: GrantFiled: September 26, 2016Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Jack T. Kavalieros, Sean T. Ma, Harold Kennel
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Publication number: 20220140076Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Inventors: Cheng-Ying HUANG, Tahir GHANI, Jack KAVALIEROS, Anand MURTHY, Harold KENNEL, Gilbert DEWEY, Matthew METZ, Willy RACHMADY, Sean MA, Nicholas MINUTILLO