Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Abstract: Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.

Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.

Abstract: One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.

Abstract: One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.

Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.

Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.

Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.

Abstract: A method can include, amplifying an analog input signal to generate an amplified analog signal; modulating the amplified analog signal into a digital data stream; filtering the digital data stream with a first digital filter to generate a first filtered data stream, and selectively changing a gain of the amplifier in response to the first filtered data stream. While the digital data stream is filtered with the first digital filter, the digital data stream is filtered with a second digital filter to generate a second filtered data stream. An output digital value corresponding to the analog input signal in response to the second filtered data stream. Corresponding systems and devices are also disclosed.

Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.

Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.

Abstract: A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal.

Abstract: A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal.

Abstract: A first portion of a programmable switched capacitor block includes a first plurality of switched capacitors and a second portion of the programmable switched capacitor block includes a second plurality of switched capacitors. A first switch associated with the first plurality of switched capacitors as well as a second switch associated with the second plurality of switched capacitors may be configured based on a type of analog function that is to be provided. The configuring of the first analog and the second analog block may include the configuring of the first switch associated with the first plurality of switched capacitors when the analog function operates on a first single ended signal and the configuring of both the first and second switches when the analog function operates on a differential signal.

Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

Abstract: An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.