Abstract: A very high speed data bus system for communication among the various functional units that may constitute a large computer system. The bus communication medium comprises a number of line pairs on the backplane, and the bus system comprises a bus control unit for arbitrating requests from a plurality of interface units or ports, there being one such port associated with each functional unit. The functional units are densely packed, that is, mounted in immediately adjacent connectors to define a populated section of the backplane in which all connectors have ports coupled thereto, and one or two unpopulated sections of the backplane in which the connectors are empty. In the populated section, the effective characteristic impedance, designated Z.sub.O ', is lower than the effective characteristic impedance, designated Z.sub.O, in the unpopulated region. A populated end of the transmission line is resistively terminated with a resistance corresponding to Z.sub.

Abstract: A very high speed data bus system for communication among the various functional units that may constitute a large computer system. The bus communication medium comprises a number of line pairs on the backplane, and the bus system comprises a bus control unit for arbitrating requests from a plurality of interface units or ports, there being one such port associated with each functional unit. The functional units are densely packed, that is, mounted in immediately adjacent connectors to define a populated section of the backplane in which all connectors have ports coupled thereto, and one or two unpopulated sections of the backplane in which the connectors are empty. In the populated section, the effective characteristic impedance, designated Z.sub.0 ', is lower than the effective characteristic impedance, designated Z.sub.0, in the unpopulated region. A populated end of the transmission line is resistively terminated with a resistance corresponding to Z.sub.

Abstract: In a high speed data bus system, each functional unit has an associated port which operates to accept all related information that makes up a communication, or if this cannot be done, to accept none of the information. More particularly, an information transfer, depending on its nature, may comprise one BIQ or more than one BIQ (a "BIQ" is a bus information quantum which is placed on the bus for one bus cycle). To implement the indivisibility of multiple-BIQ transfers, the control logic for each port includes screening circuitry responsive to the state of the port's input buffers, and further responsive to flags from the functional unit for selectively accepting or rejecting BIQ's, and further includes screening constraint circuitry to ensure that the port accepts all or none of the BIQ's that make up the transfer. Depending on the flag, the rejection may be total, or may apply only to a designated class of transfers (for example, operations).