Abstract: A voltage controlled oscillator circuit including an oscillator circuit having first and second terminals to which an external inductance is connected. A frequency control voltage (V.sub.F) is applied through a bias circuit to the second terminal for varying the center frequency. The oscillator circuit may have an AGC circuit or a modulation circuit connected to it. An output amplifier is connected with the first terminal and has an adjustable output impedance for matching the input impedance of a load circuit.

Abstract: An active dummy load substantially reduces skews for input signals of a CML or an ECL series gate by generating a selectable capacitance that adjusts the delay time of the output signal in relation to the changing of the input signal to one of two states.

Abstract: An identification circuit for use in identifying at least two integrated circuits having the same logic function but different input/output characteristics, each circuit having first and second isolated power supply conductors. A unilateral current conducting circuit having an input and an output is coupled between the first and second power supply conductors via conductive jumpers in all but one of the identifiable integrated circuits. The conductive jumpers are removed for one integrated circuit family. The other integrated circuit families have unique combinations of a resistor and at least one serially coupled diode wherein a predetermined potential is required to induce current to flow therethrough for each family. The potential of the first power supply conductor is increased in predetermined steps until current flow is detected, or a predetermined maximum potential is reached.

Abstract: A clock distribution circuit for distributing a clock signal to a plurality of other circuits, having a substantially reduced skew between the input signal and the plurality of output signals wherein signals are transmitted from an input gate to a plurality of output gates and output pads along radially disposed metalization lines. The radially disposed metalization lines are terminated at forty five degrees, thereby reducing reflections, and are of equal length for like signals.

Abstract: A multiplexer comprises a select circuit having a plurality of OR gates responsive to digital select signals. Transistors within the OR gates are collector dotted and provide a plurality of select circuit outputs to a plurality of AND gates which are also responsive to a plurality of input signals. The collector dotting of the four OR gates of the select circuit provides a multiplexer having a single gate delay of data transmission. The multiplexer consumes less current by having only a single current source for the AND gates.