Abstract: A method and system are provided for controlling clock operation in a memory that applies a test mode to test functionality of the memory which controls timing in a self-time loop using an external clock that on a rising edge triggers a main clock and on a falling edge provides a reset timer return path to reset the main clock signal. In the reset timer return path, a rising edge of the external clock triggers start of a self-time loop, and the rising edge of the external clock also controls the reset timer return path to block generation of a reference bit line (RBL) signal. In the reset timer return path, a falling edge of the external clock generates the RBL signal to provide an external clock return signal to enable an end of cycle for the self-time loop.

Abstract: A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

Abstract: A memory device includes a memory device and control circuitry. The memory array includes bitcells and bitlines connected to the bitcells. The bitcells are grouped into bitcell groups. The control circuitry is connected to the bitcell groups via the bitlines. The control circuitry adjusts connections with the bitcell groups to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations based on a half-word control signal being enabled.

Abstract: A system and method are provided for driving a dual-rail memory circuit that operates with sensing of a memory bit cell, inversion of the sense signal and level shifting in four stage delays. The system includes inversion circuitry configured to (i) receive power from a first power rail (VDDA) of the dual-rail memory, (ii) receive an output of a sense amplifier that senses a state of a bit cell of the dual-rail memory, and (iii) provide two outputs (QB, QT) limited to the first power rail VDDA. The system further includes level-shifting circuitry configured to (i) receive the two outputs of the inversion circuitry (QB, QT). (ii) receive power from a second power rail of the dual-rail memory (VDDP) and (iii) drive an output (Q) in dependence on the two outputs of the inversion circuitry (QB, QT) and limited to the second power rail VDDP which is less than the first power rail VDDA.

Abstract: Various SRAM non-clamping write driver with write-assist are disclosed, including a write driver circuitry that does not clamp the Bitlines (BLs) during the write operations, and a negative BL Write-Assist (WA) circuit that provides a negative BL boost desirable for use with high-density bit cells. When used with memories other than those having high-density bit cells, the negative BL WA improves the minimum voltage (Vmin) and frequency of operation.

Abstract: A method is provided for testing two port memory. The method includes receiving a synchronous write through (SWT) mode signal that indicates one of a functional mode of operation and a testing mode of operation of the memory, wherein the testing mode triggers bypassing of one or more read operations from bit cells of the memory identified by read address signals, and switching between the functional and testing modes of operation in dependence on the SWT mode signal. When the memory is in the testing mode of operation the circuit, receiving test data obtained from read address signals to represent a test state for the bit cells of the memory.

Abstract: A memory device includes a memory device and control circuitry. The memory array includes bitcells and bitlines connected to the bitcells. The bitcells are grouped into bitcell groups. The control circuitry is connected to the bitcell groups via the bitlines. The control circuitry adjusts connections with the bitcell groups to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations based on a half-word control signal being enabled.

Abstract: A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

Abstract: Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.

Abstract: A level shifter circuit includes a level shifter configured to receive a first clock signal associated with a first power level and generate a second clock signal associated with a second power level, wherein the second power level is greater than the first power level. The level shifter circuit further includes an input clock buffer having a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first input, wherein the second input includes the first clock signal.

Abstract: A level shifter circuit includes a level shifter configured to receive a first clock signal associated with a first power level and generate a second clock signal associated with a second power level, wherein the second power level is greater than the first power level. The level shifter circuit further includes an input clock buffer having a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first input, wherein the second input includes the first clock signal.

Abstract: A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

Abstract: Various SRAM non-clamping write driver with write-assist are disclosed, including a write driver circuitry that does not clamp the Bitlines (BLs) during the write operations, and a negative BL Write-Assist (WA) circuit that provides a negative BL boost desirable for use with high-density bit cells. When used with memories other than those having high-density bit cells, the negative BL WA improves the minimum voltage (Vmin) and frequency of operation.

Abstract: Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.

Abstract: A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

Abstract: A memory circuit system and method for using the same are provided. In one example, the memory circuit system includes a memory array, a first precharge circuit, and a second precharge circuit. The memory array writes a first set of columns of the memory array. The first precharge circuit charges bitlines of a second set of columns of the memory array while bitlines of the first set of columns discharge. The first set of columns is different from the second set of columns. The second precharge circuit charges the bitlines of the first set of columns after the memory array has finished writing the first set of columns.

Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

Abstract: A memory device having a wake-up protocol is disclosed. The memory device comprises a plurality of bitcells operative in a deep-sleep mode having corresponding bitline pairs coupled to the plurality of bitcells, a first PFET coupled between a core voltage supply and the plurality of bitcells configured to supply a core voltage to the plurality of bitcells, and a second PFET having a drain coupled to the plurality of bitcells, a source coupled to a gate of the first PFET, and a gate configured to receive a first wake signal to enable precharge of the plurality of bitcells.

Abstract: A memory device having a wake-up protocol is disclosed. The memory device comprises a plurality of bitcells operative in a deep-sleep mode having corresponding bitline pairs coupled to the plurality of bitcells, a first PFET coupled between a core voltage supply and the plurality of bitcells configured to supply a core voltage to the plurality of bitcells, and a second PFET having a drain coupled to the plurality of bitcells, a source coupled to a gate of the first PFET, and a gate configured to receive a first wake signal to enable precharge of the plurality of bitcells.

Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.