Patents by Inventor Harold Ryan
Harold Ryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10734282Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.Type: GrantFiled: September 25, 2018Date of Patent: August 4, 2020Assignee: Intel CorporationInventors: Harold Ryan Chase, Mihir K Roy, Mathew J Manusharow, Mark Hlad
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Patent number: 10312007Abstract: A method and device includes a first conductor formed on a first dielectric layer as a partial turn of a coil. A second conductor is formed on a second dielectric layer that covers the first dielectric layer and first conductor, the second conductor forming a partial turn of the coil. A vertical interconnect couples the first and second conductors to form a first full turn of the coil. The interconnect coupling can be enhanced by embedding some selective magnetic materials into the substrate.Type: GrantFiled: December 11, 2012Date of Patent: June 4, 2019Assignee: Intel CorporationInventors: Mihir K Roy, Mathew J Manusharow, Harold Ryan Chase
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Publication number: 20190027405Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.Type: ApplicationFiled: September 25, 2018Publication date: January 24, 2019Inventors: Harold Ryan Chase, Mihir K. Roy, Mathew J. Manusharow, Mark Hlad
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Patent number: 10121701Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.Type: GrantFiled: July 26, 2016Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Harold Ryan Chase, Mihir K. Roy, Mathew J. Manusharow, Mark Hlad
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Publication number: 20180291858Abstract: A system, method and circuit for providing a boost voltage with a transient operation of a vehicular start-stop system are provided. The system includes a duty cycle or current monitor to detect a change in duty cycle or current based on the transient operation; a crank time-out detector to determine whether the change in duty cycle is over a predetermined threshold; and a reset generator to generate a reset of a boost circuit that generates the boost voltage after a predetermined delay.Type: ApplicationFiled: June 15, 2018Publication date: October 11, 2018Inventors: David Ronald Fryc, Harold Ryan Macks, Mike Lees, Joe Pulls
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Patent number: 10018172Abstract: A system, method and circuit for providing a boost voltage with a transient operation of a vehicular start-stop system are provided. The system includes a duty cycle or current monitor to detect a change in duty cycle or current based on the transient operation; a crank time-out detector to determine whether the change in duty cycle is over a predetermined threshold; and a reset generator to generate a reset of a boost circuit that generates the boost voltage after a predetermined delay.Type: GrantFiled: August 27, 2014Date of Patent: July 10, 2018Assignee: Visteon Global Technologies, Inc.Inventors: David Ronald Fryc, Harold Ryan Macks, Mike Lees, Joe Pulis
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Patent number: 9741686Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.Type: GrantFiled: February 29, 2016Date of Patent: August 22, 2017Assignee: Intel CorporationInventors: Harold Ryan Chase, Mathew J Manusharow, Mihir K Roy
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Publication number: 20160336223Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventors: Harold Ryan Chase, Mihir K. Roy, Mathew J. Manusharow, Mark Hlad
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Patent number: 9406587Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.Type: GrantFiled: June 26, 2012Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Harold Ryan Chase, Mihir K. Roy, Mathew J. Manusharow, Mark Hlad
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Publication number: 20160204067Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.Type: ApplicationFiled: February 29, 2016Publication date: July 14, 2016Inventors: Harold Ryan Chase, Mathew J. Manusharow, Mihir K. Roy
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Publication number: 20160061171Abstract: A system, method and circuit for providing a boost voltage with a transient operation of a vehicular start-stop system are provided. The system includes a duty cycle or current monitor to detect a change in duty cycle or current based on the transient operation; a crank time-out detector to determine whether the change in duty cycle is over a predetermined threshold; and a reset generator to generate a reset of a boost circuit that generates the boost voltage after a predetermined delay.Type: ApplicationFiled: August 27, 2014Publication date: March 3, 2016Inventors: David Ronald Fryc, Harold Ryan Macks, Mike Lees, Joe Pulis
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Patent number: 9275975Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.Type: GrantFiled: March 28, 2014Date of Patent: March 1, 2016Assignee: Intel CorporationInventors: Harold Ryan Chase, Mathew J Manusharow, Mihir K Roy
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Publication number: 20150279813Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Inventors: Harold Ryan Chase, Mathew J. Manusharow, Mihir K. Roy
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Publication number: 20140159850Abstract: A method and device includes a first conductor formed on a first dielectric layer as a partial turn of a coil. A second conductor is formed on a second dielectric layer that covers the first dielectric layer and first conductor, the second conductor forming a partial turn of the coil. A vertical interconnect couples the first and second conductors to form a first full turn of the coil. The interconnect coupling can be enhanced by embedding some selective magnetic materials into the substrate.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Inventors: Mihir K. Roy, Mathew J. Manusharow, Harold Ryan Chase
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Publication number: 20130341772Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.Type: ApplicationFiled: June 26, 2012Publication date: December 26, 2013Inventors: Harold Ryan Chase, Mihir K. Rov, Mathew J. Manusharow, Mark Hlad
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Publication number: 20120112729Abstract: A limiter circuit includes a voltage rail having an input and an output, the input receiving an applied input voltage, a switching device in electrical communication with the voltage rail to selective control an electric current flowing through the output of the voltage rail, limiter capacitor in electrical communication with the input of the voltage rail and the switching device, wherein the limiter capacitor and the switching device are in parallel electrical communication between the input and an electrical ground, and a first resistor interposed between the limiter capacitor and the electrical ground, wherein an impedance of the resistor and the limiter capacitor define a time constant for the charging the limiter capacitor, and wherein the time constant of the limiter capacitor controls a voltage applied to the switching device and a current flowing through the output of the voltage rail.Type: ApplicationFiled: November 8, 2010Publication date: May 10, 2012Applicant: VISTEON GLOBAL TECHNOLOGIES, INC.Inventors: Daniel Robert Edwards, Viren B. Merchant, Harold Ryan Macks
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Publication number: 20070105607Abstract: An error data dumping process on a game console is described, in which a request for an error data dump may be initiated using commands mapped to a handheld game controller. The request may include parameters for customizing the resulting dump, where the parameters may identify one or more physical memory address ranges to be included in the dump. Allocated virtual memory contents may also be added to the dump data structure, as can call stack data (such as thread lists and module lists) and system information. The assembled dump data can be written to a file and uploaded, via secure communication, to a network location where it may be indexed.Type: ApplicationFiled: November 8, 2005Publication date: May 10, 2007Applicant: Microsoft CorporationInventors: Zachary Russell, Luke Timmins, Harold Ryan, Stefan Sinclair
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Patent number: 6259287Abstract: A regulated voltage supply contains a zener diode controlled by a constant current generator to maintain the zener voltage at a constant level regardless of the swings of the voltage input to the diode. A current amplifier responds to the constant current generator to maintain the output voltage of the regulated voltage supply at the value of the zener voltage regardless of the demands of the load. A low voltage inhibit circuit responds to the magnitude of the input voltage and the magnitude of the voltage on the zener diode to generate a binary voltage signal for inhibiting the operation of a load such as a microcomputer when the voltage regulator is below the zener voltage level and the input is below the desired voltage.Type: GrantFiled: July 20, 2000Date of Patent: July 10, 2001Assignee: Visteon Global Technologies, Inc.Inventor: Harold Ryan Macks
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Patent number: 6242821Abstract: A passive processing circuit for processing a ground side switch closure to a CMOS input (20) of an MCU, particularly useful in a D.C. electrical system where ground offsets may occur, such as in an automotive vehicle. Three resistors (R1, R2, R3) are connected between supply and ground potentials of a D.C. power supply voltage (10). The junction of two (R1, R2) connects to an output (16) of a grounded input switch (12). The junction of two (R2, R3) connects to the CMOS input (20). A fourth resistor (R4) connects between the bi-directional input/output (22) of the MCU and the junction of the second and third resistors. The MCU executes an algorithm that selectively allows and disallows the resistor (R4) to coact with the second and third resistors. The circuit provides a cost-efficient solution for extending the range of supply line voltage over which a CMOS input can correctly read a switch closure.Type: GrantFiled: June 7, 1999Date of Patent: June 5, 2001Assignee: Visteon Global Technologies, Inc.Inventor: Harold Ryan Macks
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Patent number: 6239982Abstract: In one embodiment of the present invention, an electronic device comprises a circuit board having a first side and a second side and having circuit traces formed only on the first side. The electronic device further includes a voltage regulator providing a regulated voltage via a regulated voltage output terminal and having a regulated voltage return terminal. Additionally, the electronic device includes a microcontroller mounted to the first side of the circuit board and having a plurality of regulated voltage input terminals and corresponding microcontroller voltage return terminals. The electronic device also comprises a bus comprising a first circuit trace coupled to the regulated voltage output terminal and a second circuit trace coupled to the regulated voltage return terminal, the first circuit trace and the second circuit trace running substantially parallel to one another.Type: GrantFiled: June 23, 1999Date of Patent: May 29, 2001Assignee: Visteon Global Technologies, Inc.Inventors: Erich Bozzer, Harold Ryan Macks, Jarek Tracz, Roman Jaroslaw Los