Patents by Inventor Harold Scholz
Harold Scholz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7808855Abstract: In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a corresponding incoming bit stream from a corresponding data I/O block. The FIFO controller controls operations of the one or more FIFOs, such that (i) bits from the corresponding data I/O block are written into the at least one FIFO using a FIFO write clock that is based on an incoming clock signal and (ii) bits are read out from the at least one FIFO using a FIFO read clock that is based on a local reference clock signal.Type: GrantFiled: August 10, 2009Date of Patent: October 5, 2010Assignee: Lattice Semiconductor CorporationInventors: Fulong Zhang, Harold Scholz, Larry Fenstermaker, John Schadt
-
Patent number: 7616029Abstract: In one embodiment of the invention, a bias signal monitor has two signal comparators that compare two (power supply) voltages at two different bias points and a logic circuit that processes the outputs from the two signal monitors to generate a bias signal monitor output signal. The logic circuit implements hysteresis-based processing such that (1) if both signal comparators are active (indicating that a first voltage is greater than the second voltage relative to both bias points), then the monitor output is active, (2) if both signal comparators are inactive (indicating that the first voltage is not greater than the second voltage relative to either bias point), then the monitor output is inactive, and (3) if one signal comparator is active and the other is inactive, then the monitor output keeps its previous value. This hysteresis characteristic prevents relatively small oscillations between the voltages from changing the monitor output.Type: GrantFiled: October 9, 2007Date of Patent: November 10, 2009Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Phillip Johnson, John Schadt, Harold Scholz
-
Patent number: 7573770Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock and a data lane having a plurality of bit lines from the external device. The distributed FIFO architecture comprise a FIFO for each bit line and a FIFO controller. Under control of the FIFO controller, data is written into each FIFO using a FIFO write clock based on the strobe clock, while data is read out from each FIFO using a FIFO read clock based on a local reference clock of the integrated circuit. The distributed FIFO architecture is designed to handle a range of possible phase differences between the FIFO write and read clocks to safely convert from the asynchronous, non-continuous strobe domain to a local continuous clock domain.Type: GrantFiled: July 16, 2007Date of Patent: August 11, 2009Assignee: Lattice Semiconductor CorporationInventors: Fulong Zhang, Harold Scholz, Larry Fenstermaker, John Schadt
-
Patent number: 7554357Abstract: In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.Type: GrantFiled: February 3, 2006Date of Patent: June 30, 2009Assignee: Lattice Semiconductor CorporationInventors: Zheng (Jeff) Chen, Barry Britton, Harold Scholz
-
Patent number: 7429875Abstract: A logic circuit is disclosed that is tolerant of logic signals with voltages different from the voltage of the logic circuit power supply. In one embodiment, the logic circuit has an inverting amplifier therein, the amplifier having at least one input and an output and is powered by the power supply. A first transistor, in responsive to the output of the amplifier, biases the input of the amplifier to assure substantially no static current flows through the amplifier when a logic-low is present on the amplifier output. A second transistor couples at least one logic input of the logic circuit to the input of the amplifier. In one embodiment, the second transistor impedes static current flow from the first transistor, through the second transistor, to the logic input. Various other embodiments of the logic circuit include a latch/flip-flop, multiplexer, and a complex logic gate.Type: GrantFiled: December 13, 2006Date of Patent: September 30, 2008Assignee: Lattice Semiconductor CorporationInventors: Larry R. Fenstermaker, Harold Scholz
-
Publication number: 20080143380Abstract: A logic circuit is disclosed that is tolerant of logic signals with voltages different from the voltage of the logic circuit power supply. In one embodiment, the logic circuit has an inverting amplifier therein, the amplifier having at least one input and an output and is powered by the power supply. A first transistor, in responsive to the output of the amplifier, biases the input of the amplifier to assure substantially no static current flows through the amplifier when a logic-low is present on the amplifier output. A second transistor couples at least one logic input of the logic circuit to the input of the amplifier. In one embodiment, the second transistor impedes static current flow from the first transistor, through the second transistor, to the logic input. Various other embodiments of the logic circuit include a latch/flip-flop, multiplexer, and a complex logic gate.Type: ApplicationFiled: December 13, 2006Publication date: June 19, 2008Inventors: Larry R. Fenstermaker, Harold Scholz
-
Publication number: 20070182445Abstract: In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.Type: ApplicationFiled: February 3, 2006Publication date: August 9, 2007Inventors: Zheng Chen, Barry Britton, Harold Scholz
-
Publication number: 20070109880Abstract: When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between rising and falling edges of a reference clock signal associated with the data bus, which sampling time corresponds to a 90-degree phase shift of the reference clock signal. In one embodiment of the invention, a delay count generator determines a delay value corresponding to a quarter cycle (i.e., 90 degrees) of the reference clock signal. In making this determination, a counter counts the number of clock cycles of an internally generated, relatively high-frequency clock signal, where the number corresponds to a specified portion (e.g., one half) of a period of a divided-down version of the reference clock signal. That number can then be used to generate the 90-degree delay value.Type: ApplicationFiled: November 17, 2005Publication date: May 17, 2007Inventors: Fulong Zhang, Harold Scholz
-
Patent number: 7132903Abstract: A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.Type: GrantFiled: July 3, 2003Date of Patent: November 7, 2006Assignee: Lattice Semiconductor CorporationInventors: Phillip Johnson, Gary Powell, Harold Scholz
-
Patent number: 7034596Abstract: Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.Type: GrantFiled: February 11, 2003Date of Patent: April 25, 2006Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Harold Scholz, Barry K. Britton
-
Patent number: 7009423Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.Type: GrantFiled: May 20, 2005Date of Patent: March 7, 2006Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Fulong Zhang, Harold Scholz
-
Patent number: 6952115Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.Type: GrantFiled: July 3, 2003Date of Patent: October 4, 2005Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Fulong Zhang, Harold Scholz
-
Patent number: 6943583Abstract: A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).Type: GrantFiled: September 25, 2003Date of Patent: September 13, 2005Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Mou C. Lin, Harold Scholz, Arifur Rahman
-
Patent number: 6903574Abstract: Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial memory interface is associated with each special functional block within a programmable logic device to provide access to configuration memory cells of the special functional block.Type: GrantFiled: July 29, 2003Date of Patent: June 7, 2005Assignee: Lattice Semiconductor CorporationInventors: Zheng (Jeff) Chen, Fulong Zhang, Harold Scholz
-
Patent number: 6873187Abstract: An electronic circuit includes delay selection units each associated with a flip-flop or other circuit element. The delay selection unit for a given one of the circuit elements is coupled between a source of a clock or other signal and a corresponding input of the circuit element, and is controllable to provide one of a number of selectable delays for the signal. One or more of the delay selection units are controlled so as to select a particular one of the selectable delays for each of the units. In an illustrative embodiment, the particular delays may be determined at least in part based on the solution of an integer nonlinear program in which the plurality of delays for a given one of the delay selection units are arranged substantially in a monotonically increasing manner and each of at least a subset of the selectable delays for the given one of the delay selection units is specified by upper and lower bounds on the corresponding delay.Type: GrantFiled: March 27, 2003Date of Patent: March 29, 2005Assignee: Lattice Semiconductor CorporationInventors: William Andrews, Barry Britton, Xiaotao Chen, John P. Fishburn, Harold Scholz
-
Publication number: 20050024085Abstract: Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial memory interface is associated with each special functional block within a programmable logic device to provide access to configuration memory cells of the special functional block.Type: ApplicationFiled: July 29, 2003Publication date: February 3, 2005Inventors: Zheng (Jeff) Chen, Fulong Zhang, Harold Scholz
-
Patent number: 6812869Abstract: An input/output (I/O) circuit bank is disclosed, in accordance with one embodiment, having programmable I/O circuits configurable to support I/O interface standards for single-ended and differential signaling. The associated pads of one or more of the I/O circuits may be utilized to provide an external reference signal via a pass transistor onto an internal bus for use by the remainder of the I/O circuits. The pass transistors may be designed to function as lowpass filters to limit the amount of noise that passes through them.Type: GrantFiled: February 13, 2003Date of Patent: November 2, 2004Assignee: Lattice Semiconductor CorporationInventors: Arifur Rahman, Harold Scholz
-
Publication number: 20040155690Abstract: Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.Type: ApplicationFiled: February 11, 2003Publication date: August 12, 2004Applicant: Lattice Semiconductor CorporationInventors: William B. Andrews, Harold Scholz, Barry K. Britton
-
Patent number: 6700823Abstract: Systems and methods provide common mode termination for input/output circuits. For example, common mode termination may be provided to a bank of input/output circuits by programmably coupling a bus to each pair of input/output circuits. The bus provides a path to ground for common mode signals through a capacitor or, alternatively, the bus may be designed to provide or assist in providing the necessary capacitance.Type: GrantFiled: October 30, 2002Date of Patent: March 2, 2004Assignee: Lattice Semiconductor CorporationInventors: Arifur Rahman, Harold Scholz