Patents by Inventor Harold W. Kennel

Harold W. Kennel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446685
    Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Matthew V. Metz, Harold W. Kennel, Gilbert Dewey, Willy Rachmady, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20190267289
    Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.
    Type: Application
    Filed: September 30, 2016
    Publication date: August 29, 2019
    Applicant: Intel Corporation
    Inventors: Gilbert DEWEY, Matthew V. METZ, Sean T. MA, Cheng-Ying HUANG, Tahir GHANI, Anand S. MURTHY, Harold W. KENNEL, Nicholas G. MINUTILLO, Jack T. KAVALIEROS, Willy RACHMADY
  • Patent number: 10388764
    Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Matthew V. Metz, Gilbert Dewey, Willy Rachmady, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20190198658
    Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.
    Type: Application
    Filed: September 29, 2016
    Publication date: June 27, 2019
    Applicant: INTEL CORPORATION
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Anand S. Murthy, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz, Sean T. Ma
  • Publication number: 20190189753
    Abstract: Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: Matthew Metz, Gilbert Dewey, Harold W. Kennel, Cheng-Ying Huang, Sean T. Ma, Willy Rachmady
  • Publication number: 20190189794
    Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.
    Type: Application
    Filed: February 23, 2019
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: CHANDRA S. MOHAPATRA, ANAND S. MURTHY, GLENN A. GLASS, TAHIR GHANI, WILLY RACHMADY, JACK T. KAVALIEROS, GILBERT DEWEY, MATTHEW V. METZ, HAROLD W. KENNEL
  • Publication number: 20190189464
    Abstract: Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 20, 2019
    Inventors: Aaron D. Lilak, Harold W. Kennel, Patrick Morrow, Rishabh Mehandru, Stephen M. Cea
  • Publication number: 20190115466
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 18, 2019
    Applicant: INTEL CORPORATION
    Inventors: STEPHEN M. CEA, ROZA KOTLYAR, HAROLD W. KENNEL, GLENN A. GLASS, ANAND S. MURTHY, WILLY RACHMADY, TAHIR GHANI
  • Patent number: 10243078
    Abstract: An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani, Anand S. Murthy, Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass
  • Patent number: 10229997
    Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: March 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros, Gilbert Dewey, Matthew V. Metz, Harold W. Kennel
  • Publication number: 20190035897
    Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 31, 2019
    Inventors: Chandra S. MOHAPATRA, Harold W. KENNEL, Glenn A. GLASS, Will RACHMADY, Gilbert DEWEY, Jack T. KAVALIEROS, Anand S. MURTHY, Tahir GHANI, Matthew V. METZ, Sean T. MA
  • Publication number: 20190035893
    Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
    Type: Application
    Filed: October 1, 2018
    Publication date: January 31, 2019
    Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
  • Patent number: 10186580
    Abstract: Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jack T. Kavalieros, Robert S. Chau, Harold W. Kennel
  • Patent number: 10153372
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 11, 2018
    Assignee: INTEL CORPORATION
    Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Willy Rachmady, Tahir Ghani
  • Publication number: 20180331183
    Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2015
    Publication date: November 15, 2018
    Inventors: AARON D. LILAK, RISHABH MEHANDRU, HAROLD W. KENNEL, PAUL B. FISCHER, STEPHEN M. CEA
  • Publication number: 20180323310
    Abstract: Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.
    Type: Application
    Filed: December 23, 2014
    Publication date: November 8, 2018
    Applicant: Intel Corporation
    Inventors: HAROLD W. KENNEL, MATTHEW V. METZ, WILLY RACHMADY, GILBERT DEWEY, CHANDRA S. MOHAPATRA, ANAND S. MURTHY, JACK T. KAVALIEROS, TAHIR GHANI
  • Patent number: 10109711
    Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Stephen M Cea, Roza Kotlyar, Harold W Kennel, Anand S Murthy, Glenn A Glass, Kelin J Kuhn, Tahir Ghani
  • Patent number: 10103263
    Abstract: Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Van H. Le, Harold W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack Kavalieros, Niloy Mukherjee
  • Publication number: 20180254332
    Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.
    Type: Application
    Filed: September 25, 2015
    Publication date: September 6, 2018
    Applicant: Intel Corporation
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Matthew V. Metz, Gilbert Dewey, Willy Rachmady, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20180248028
    Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 30, 2018
    Applicant: Intel Corporation
    Inventors: Chandra S. Mohapatra, Matthew V. Metz, Harold W. Kennel, Gilbert Dewey, Willy Rachmady, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani