Patents by Inventor Harold Wade Cain, III

Harold Wade Cain, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8572341
    Abstract: A method, a system and a computer program product for handling speculative stores. The system determines when a speculative store buffer is not full. An indicator is generated when the speculative store buffer is not full, and the speculative stores are input into the speculative store buffer. When the speculative store buffer is full, a full buffer indicator is generated. Speculative stores prevented from entering the speculative store buffer are overflow stores. The overflow list is searched to determine whether one or more addresses of the overflow stores are present in the overflow list. When one or more addresses of the overflow stores are not present in the overflow list, the overflow stores are stored in the overflow list.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Colin B. Blundell, Harold Wade Cain, III, Gheorghe C. Cascaval, Maged Milad Michael
  • Publication number: 20130262424
    Abstract: Systems, methods, and products for database system transaction management are provided herein. One aspect provides for annotating via a computing device at least one data object residing on the computing device utilizing at least one transaction tag, the at least one transaction tag being configured to indicate a status of an associated data object; processing at least one database transaction utilizing a transactional memory process, wherein access to the at least one data object is determined based on the status of the at least one data object; and updating the status of the at least one data object responsive to an attempted access of the at least one data object by the at least one database transaction. Other embodiments and aspects are also described herein.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Wade Cain, III, Donna N. Dillenberger, Michel H.T. Hack, Hong Min, Gong Su, James Zu-Chia Teng
  • Publication number: 20130159678
    Abstract: A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: Toshihiko Koju, Takuya Nakaike, Ali Ijaz Sheikh, Harold Wade Cain, III, Maged M. Michael
  • Patent number: 8392694
    Abstract: A method, system and computer program product for issuing one or more software initiated operations for creating a checkpoint of a register file and memory, and for restoring a register file and memory to the checkpointed state. At the execution of a checkpoint operation, the system returns a condition code indicating success or failure. When the condition code is set equal to one, one or more checkpoints are initiated. Contents of the register file and gated store buffer are stored each time the one or more checkpoints are initiated. When the checkpoint is created, the system notifies software when a hardware checkpoint capacity has been reached. One or more of the software checkpoint, hardware checkpoint, and handler checkpoint are utilized to provide a more precise point of restoration. During software execution, the register file and gated store buffer can be restored as defined by the one or more previous checkpoints.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Colin B. Blundell, Harold Wade Cain, III, Gheorghe C. Cascaval, Maged Milad Michael
  • Publication number: 20130007374
    Abstract: A dual-mode prefetch system for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags identifying the data stored in the data array; a checkpoint tag array storing data identification information; and a cache controller with prefetch logic.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Wade Cain, III, Jong-Deok Choi
  • Patent number: 8341352
    Abstract: A dual-mode prefetch mechanism for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags for identifying the data stored in the data array; a set of checkpoint tags for storing data identification; a cache controller including prefetch logic, the prefetch logic including a checkpoint prefetch controller and a checkpoint prefetch operator.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Harold Wade Cain, III, Jong-Deok Choi
  • Publication number: 20120303857
    Abstract: A cache management method using checkpoint tags in checkpoint mode includes steps of: receiving a request to save data; fetching at least one cache block including the data from cache memory; writing the data from the at least one cache block into the data array; writing a physical address and metadata of the cache block into an array of cache memory tags; and upon receipt of a restore request: fetching an identifier for the at least one cache block stored in the checkpoint tag array; reloading the cache memory with the at least one cache block in the checkpoint tag array; and switching to normal mode.
    Type: Application
    Filed: August 2, 2012
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Wade Cain, III, Jong-Deok Choi
  • Patent number: 8131894
    Abstract: A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Harold Wade Cain, III, Rui Hou, Xiaowei Shen, Huayong Wang
  • Patent number: 8122438
    Abstract: Computer implemented method, system and computer usable program code for profiling the execution of an application that is both space- and time-efficient and highly accurate. A computer implemented method for profiling the execution of an application includes sampling execution characteristics of the application at a plurality of sampling points to provide samples, and deriving a calling context of the samples. The application is continuously executed between sampling points while additional profiling data is gathered.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Harold Wade Cain, III, Jong-Deok Choi, Mauricio Jose Serrano, Xiaotong Zhuang
  • Patent number: 7818722
    Abstract: Computer implemented method, system and computer usable program code for profiling the execution of an application that is both space- and time-efficient and highly accurate. A computer implemented method for profiling the execution of an application includes sampling execution characteristics of the application at a plurality of sampling points to provide samples, and deriving a calling context of the samples. The application is continuously executed between sampling points while additional profiling data is gathered.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Harold Wade Cain, III, Jong-Deok Choi, Mauricio Jose Serrano, Xiaotong Zhuang
  • Publication number: 20100138571
    Abstract: A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.
    Type: Application
    Filed: November 23, 2009
    Publication date: June 3, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Wade Cain, III, Rui Hou, Xiaowei Shen, Huayong Wang
  • Publication number: 20090113132
    Abstract: A computer-implemented method of cache replacement includes steps of: determining whether each cache block in a cache memory is a read or a write block; augmenting metadata associated with each cache block with an indicator of the type of access; receiving an access request resulting in a cache miss, the cache miss indicating that a cache block will need to be replaced; examining the indicator in the metadata of each cache block for determining a probability that said cache block will be replaced; and selecting for replacement the cache block with the highest probability of replacement.
    Type: Application
    Filed: October 24, 2007
    Publication date: April 30, 2009
    Applicant: International Business Machines Corporation
    Inventors: Harold Wade Cain, III, Jong-Deok Choi, Mauricio J. Serrano
  • Publication number: 20080288926
    Abstract: Computer implemented method, system and computer usable program code for profiling the execution of an application that is both space-and time-efficient and highly accurate. A computer implemented method for profiling the execution of an application includes sampling execution characteristics of the application at a plurality of sampling points to provide samples, and deriving a calling context of the samples. The application is continuously executed between sampling points while additional profiling data is gathered.
    Type: Application
    Filed: June 18, 2008
    Publication date: November 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINE CORPORATION
    Inventors: Harold Wade Cain, III, Jong-Deok Choi, Mauricio Jose Serrano, Xiaotong Zhuang
  • Publication number: 20080263257
    Abstract: A dual-mode prefetch mechanism for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags for identifying the data stored in the data array; a set of checkpoint tags for storing data identification; a cache controller including prefetch logic, the prefetch logic including a checkpoint prefetch controller and a checkpoint prefetch operator.
    Type: Application
    Filed: April 17, 2007
    Publication date: October 23, 2008
    Applicant: International Business Machines Corporation
    Inventors: Harold Wade Cain III, Jong-Deok Choi