Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions (20, 22) on both lateral sides of this device body (17). These lateral regions (20, 22) are formed from a second semiconductor material. A dielectric layer (28) is formed over both lateral regions (20, 22) and the device body (17), while an anode layer (30) is formed over the dielectric layer in an area defined by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions (20, 22) on both lateral sides of this device body (17). These lateral regions (20, 22) are formed from a second semiconductor material. A dielectric layer (28) is formed over both lateral regions (20, 22) and the device body (17), while an anode layer (30) is formed over the dielectric layer in an area defmed by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to iff, the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The capacitor structure includes an elongated device body (17) formed from a first semiconductor material. This device body (17) is bordered on both lateral sides by lateral regions (20, 22) formed from a second semiconductor material. A dielectric layer (28) overlays both lateral regions (20, 22) and the device body (17), while an anode layer (30) overlays the dielectric layer in an area defined by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.