Patents by Inventor Haroon Ahmed

Haroon Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100088350
    Abstract: The subject disclosure relates to a method and system for packaging a post-processed definition of a programming module. Contents of a constraint-based and/or order-independent execution model are received, in which the contents include a declarative source code. The contents are stored into an extensible storage abstraction such that the source code is stored in a declarative format. Metadata describing attributes of the contents stored in the extensible storage abstraction is also defined. A file is then created, which includes the extensible storage abstraction and the metadata.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 8, 2010
    Applicant: MICROSOFT CORPORATION
    Inventors: Haroon Ahmed, Chris Anderson, Steve Antoch
  • Patent number: 7505994
    Abstract: Various embodiments are disclosed relating to binding an application to one or more nodes of a tree (e.g., XML tree or XML document). According to an example embodiment, a tree path navigator (e.g., XPath navigator) may be invoked or called to dynamically evaluate a tree path expression to track one or more nodes identified by the expression. In another example embodiment, a notification interface may be provided for one or more nodes in the tree to provide a change notification when one of the nodes is modified. The application may be notified of a change to any node identified by the tree path expression.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: March 17, 2009
    Assignee: Microsoft Corporation
    Inventors: Haroon Ahmed, Laurent Mollicone
  • Publication number: 20070150504
    Abstract: Various embodiments are disclosed relating to binding an application to one or more nodes of a tree (e.g., XML tree or XML document). According to an example embodiment, a tree path navigator (e.g., XPath navigator) may be invoked or called to dynamically evaluate a tree path expression to track one or more nodes identified by the expression. In another example embodiment, a notification interface may be provided for one or more nodes in the tree to provide a change notification when one of the nodes is modified. The application may be notified of a change to any node identified by the tree path expression.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Applicant: Microsoft Corporation
    Inventors: Haroon Ahmed, Laurent Mollicone
  • Publication number: 20070038985
    Abstract: The subject disclosure pertains to computer programming languages and translation or conversion thereof. Rather than a complicated semantics preserving translation or conversion from a first source language to a second target language, the conversion can be one of syntax. The conversion can be accomplished, for example, via employment of a map that defines the relation between the syntax of the first language and the second language. The semantics of at least a part of the first language can be defined by the second target language. Thus, the first language can be open-ended and/or semantically extensible based on the second language.
    Type: Application
    Filed: August 10, 2005
    Publication date: February 15, 2007
    Applicant: Microsoft Corporation
    Inventors: Henricus Meijer, Avner Aharoni, Haroon Ahmed, Todd Pfleiger
  • Patent number: 6771012
    Abstract: Apparatus for producing a flux of charge carriers that may be used in many applications including imaging and lithography comprises an electron source which includes an emitter with a tip radius of about one nanometer and a closely configured extractor, together with a specimen for receiving an electron beam from the source. The apparatus may operate in air under atmospheric conditions and at a much reduced operating voltage.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: August 3, 2004
    Assignee: Hitachi Europe, Ltd.
    Inventors: Haroon Ahmed, David Hasko, Alex Driskill-Smith, David Arfon Williams
  • Patent number: 6753568
    Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: June 22, 2004
    Assignee: Hitachi, LTD.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshihiko Sato, Toshikazu Shimada, Haroon Ahmed
  • Publication number: 20010040215
    Abstract: Apparatus for producing a flux of charge carriers that may be used in many applications including imaging and lithography comprises an electron source which includes an emitter with a tip radius of about one nanometer and a closely configured extractor, together with a specimen for receiving an electron beam from the source. The apparatus may operate in air under atmospheric conditions and at a much reduced operating voltage.
    Type: Application
    Filed: March 12, 2001
    Publication date: November 15, 2001
    Inventors: Haroon Ahmed, David Hasko, Alex Driskill-Smith, David Arfon Williams
  • Patent number: 6088604
    Abstract: A superconductor-normal conductor junction device comprises first and second regions (1, 3) of normal material forming first and second junctions with a superconducting material (2), the Fermi level of the first region of normal material being so arranged relative to a given energy level in the superconducting material that charge carriers in the first normal material undergo Andreev reflection at the first junction, resulting in pairs of the charge carriers entering said given energy level in the superconducting material, and the Fermi level of the second region of normal material being so arranged relative to said given level in the superconducting material that said charge carriers conduct from the superconducting material through the second region.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: July 11, 2000
    Assignee: Hitachi, Ltd.
    Inventors: David Arfon Williams, Adrian Michael Marsh, Haroon Ahmed, Bruce William Alphenaar
  • Patent number: 5997958
    Abstract: Nanometre scale particles (3) e.g. of Au are deposited on a Si substrate (2) with a SiO.sub.2 surface layer (1) provided with receptor sites (4) of a first electrical polarity by treatment with APTMS solution. The Au particles (3) have a surface charge (5) of a second opposite polarity e.g from surface adsorbed citrate ions, such that they are attracted to the surface sites on the substrate. The deposited Au particles are then released from the surface sites such that the particles move over the substrate and coalesce into a low dimensional aggregated structure. The aggregated structure may form at a surface irregularity on the surface of the substrate. The structure may be used in a quantum electronic device such as a single electron transistor.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: December 7, 1999
    Assignee: Hitachi Europe Limited
    Inventors: Toshihiko Sato, Haroon Ahmed
  • Patent number: 5952692
    Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si.sub.3 N.sub.4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: September 14, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshihiko Sato, Toshikazu Shimada, Haroon Ahmed
  • Patent number: 5677637
    Abstract: A memory device includes a memory node (2) to which is connected a tunnel barrier configuration such that the node exhibits first and second quantized memory states for which the level of stored charge is limited by Coulomb Blockade and a surplus or shortfall of a small number of electrons for example ten electrons or even a single electron can be used to represent quantized memory states. A series of the nodes N0-N3 that are interconnected by tunnel barriers D can be arranged as a logic device. Clock waveforms V1-V3 applied to clock lines C1 1-C1 3 selectively alter the probability of charge carriers passing through the tunnel diodes D from node to node. An output device, typically a Coulomb blockade electrometer provides an output logical signal indicative of the logical state of node N3. Arrays of separately addressable memory cells M.sub.mn are also described, that utilize gated multiple tunnel junctions (MTJs) as their barrier configurations.
    Type: Grant
    Filed: February 27, 1996
    Date of Patent: October 14, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Haroon Ahmed, Julian D. White
  • Patent number: 5191213
    Abstract: The structure of a multilayered integrated circuit is determined by removing successive layers of the circuit. Following removal of each layer, the revealed surface is scanned by an electron beam. The intensity of backscattered or secondary electrons is detected by a first or second detector respectively. From the detected electron intensities, image processing circuitry derives a representation of the integrated circuit surface scanned. Where the surface of the integrated circuit is a flat layer of semiconductor substrate material having implanted doped areas, the surface is covered with a metallisation layer providing a Schottky barrier junction with the doped areas. Electron beam scanning of the metallisation layer induces a current at this junction which is monitored and processed to derive a representation of the outline of the doped implanted areas.
    Type: Grant
    Filed: July 5, 1991
    Date of Patent: March 2, 1993
    Assignee: Olivetti Systems & Networks S.r.l.
    Inventors: Haroon Ahmed, Simon Blythe, Beatrice Fraboni
  • Patent number: 4649316
    Abstract: A system for incorporation in ion-beam equipment to provide ion species filtering and optional ion beam blanking. The system has four magnets arranged on an optical axis. In between the two center magnets is arranged a plate having an off-axis aperture. The ion beam is caused to converge to a focus on a midplane in which the aforesaid plate is situated. When the magnets are energized, the ion beam is caused to bend by an amount depending upon the charge-to-mass ratio of the ion species within the beam. If constructed correctly, the aperture can thus be arranged to pass only a single ion species, the remainder colliding with and being absorbed by the plate. Beam blanking may optionally be achieved by blanking plates which may be used to deflect the ion beam in such a way that the resultant focal point of the ion beam is displaced away from the aperture so that the whole ion beam is blanked off. Astigmatism introduced into the system may be reduced or eliminated by the use of octopole electrode sets.
    Type: Grant
    Filed: September 19, 1983
    Date of Patent: March 10, 1987
    Assignee: Dubilier Scientific Limited
    Inventors: John R. A. Cleaver, Haroon Ahmed
  • Patent number: 4338508
    Abstract: Apparatus and methods for inscribing workpieces for the fabrication of masks and direct fabrication of microcircuits are described. The invention is primarily concerned with correcting for positional errors and to this end two coaxial beams (20,32) are directed towards a worktable from opposite sides thereof, the beam (20) serving as the scribing beam and the beam (32), operating in a reading mode, serving to read positional information and generate positional information and appropriate error signals for correcting the point of impact of the beam (20) with the surface of the substrate to be inscribed (28,46). In one embodiment the table (10) is solid and two layers of substrate are used on opposite surfaces of the table (10). The lower substrate (30) constitutes a master substrate which can be left in position while a large number of virgin substrates are exposed on the upper surface of the table (10).
    Type: Grant
    Filed: December 2, 1980
    Date of Patent: July 6, 1982
    Inventors: Geraint A. C. Jones, Haroon Ahmed