Abstract: A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.

Abstract: A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

Abstract: A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor device in the processing chamber without the presence of oxygen.

Abstract: A method of forming a memory device includes forming a memory stack on a substrate. The memory stack includes an alumina layer acting as an intergate dielectric layer. A transistor is formed on the substrate in an area separate from the memory stack. The transistor is formed to include thin gate oxide via a dry oxidation technique and a gate layer on the thin gate oxide. The thin gate oxide is formed without subjecting the thin gate oxide to thermal annealing with N2O.

Abstract: A semiconductor device includes a substrate that further includes source, drain and channel regions. The device may further include a bottom oxide layer formed upon the substrate, a charge storage layer formed upon the bottom oxide layer, and a steam oxide layer thermally grown upon the charge storage layer. The device may also include an alumina oxide layer formed upon the steam oxide layer and a gate electrode formed upon the alumina oxide layer.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises a tunnel oxide layer, where the tunnel oxide layer is situated on the substrate. The structure further comprises a floating gate situated on the tunnel oxide layer, where the floating gate comprises nitrogen. The floating gate may further comprise polysilicon and may be situated in a floating gate flash memory cell, for example. The nitrogen may suppress oxide growth at first and second end regions of the tunnel oxide layer, for example. The nitrogen may be implanted in the floating gate, for example, at a concentration of between approximately 1013 atoms per cm2 and approximately 1015 atoms per cm2. According to this exemplary embodiment, the structure further comprises an ONO stack situated over the floating gate. The structure may further comprise a control gate situated over the ONO stack.

Abstract: A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

Abstract: A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask, thereby increasing the width of the substrate under the active areas and increasing Weff for the device.