Patents by Inventor Harpreet Sachar
Harpreet Sachar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240082507Abstract: A cassette for a drug delivery device is described that includes a sleeve, a syringe having a barrel disposed in the sleeve, and a plunger-stopper slidably disposed within the barrel. The cassette further includes a spacer that is configured to be coupled to the sleeve. The cassette can form a part of an apparatus for injection of a therapeutic product along with a drug delivery device.Type: ApplicationFiled: October 7, 2020Publication date: March 14, 2024Inventors: Samin Akbari, Azita Rahbari, Sunitha Dasoju, Andrew Coles, Jerome Olivas, Michele Macchi, Desheng Yin, Harpreet Sachar, Alireza Ashani, Angelo Tosarini, Antonio Antonini
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Publication number: 20220184318Abstract: A cassette for a drug delivery device is described that includes a sleeve, a syringe having a barrel disposed in the sleeve, and a plunger-stopper slidably disposed within the barrel. An end cap is adapted to couple to the sleeve to secure the syringe in the sleeve. The cassette further includes a spacer that is sized to be slidably moved within the barrel and the spacer is disposed distal to the plunger-stopper to be engaged by a plunger rod to slide within the barrel and engage the plunger-stopper. In some forms, the spacer can be coupled to the end cap.Type: ApplicationFiled: April 10, 2020Publication date: June 16, 2022Inventors: Azita Rahbari, Sunitha Dasoju, Angelo Tosarini, Antonio Antonini, Julian Jazayeri, Harpreet Sachar, Andrew Coles, Desheng Yin, Alireza Ashani
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Patent number: 8802537Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.Type: GrantFiled: July 27, 2005Date of Patent: August 12, 2014Assignee: Spansion LLCInventors: Yider Wu, Unsoon Kim, Kuo-Tung Chang, Harpreet Sachar
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Patent number: 8642441Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: December 15, 2006Date of Patent: February 4, 2014Assignee: Spansion LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Harpreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 8143661Abstract: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.Type: GrantFiled: October 10, 2006Date of Patent: March 27, 2012Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Takayuki Maruyama, Hidehiko Shiraiwa, Kuo-Tung Chang, Lei Xue, Meng Ding, Amol Ramesh Joshi, YouSeok Suh, Harpreet Sachar
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Patent number: 8119477Abstract: A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.Type: GrantFiled: August 31, 2006Date of Patent: February 21, 2012Assignee: Spansion LLCInventors: Hidehiko Shiraiwa, YouSeok Suh, Harpreet Sachar, Satoshi Torii
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Patent number: 7863128Abstract: A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a third dielectric layer formed over the second dielectric layer. The third dielectric layer may have a high dielectric constant and may be deposited at a relatively high temperature. A control gate may be formed over the third dielectric layer.Type: GrantFiled: February 4, 2005Date of Patent: January 4, 2011Assignees: Spansion LLC, GLOBALFOUNDRIES, Inc.Inventors: Joong Jeon, Takashi Whitney Orimoto, Robert B. Ogle, Harpreet Sachar, Wei Zheng
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Patent number: 7675104Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.Type: GrantFiled: July 31, 2006Date of Patent: March 9, 2010Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Amol Ramesh Joshi, Harpreet Sachar, YouSeok Suh, Shenqing Fang, Chih-Yuh Yang, Lovejeet Singh, David H. Matsumoto, Hidehiko Shiraiwa, Kuo-Tung Chang, Scott A. Bell, Allison Holbrook, Satoshi Torii
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Publication number: 20080150011Abstract: A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.Type: ApplicationFiled: December 18, 2007Publication date: June 26, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Simon Siu-Sing Chan, Lei Xue, YouSeok Suh, Amol Ramesh Joshi, Hidehiko Shiraiwa, Harpreet Sachar, Kuo-Tung Chang, Connie Pin Chin Wang, Paul R. Besser, Shenqing Fang, Meng Ding, Takashi Orimoto, Wei Zheng, Fred TK Cheung
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Publication number: 20080142874Abstract: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.Type: ApplicationFiled: December 16, 2006Publication date: June 19, 2008Applicants: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Hidehiko Shiraiwa, Takayuki Maruyama, Kuo-Tung Chang, YouSeok Suh, Amol Ramesh Joshi, Harpreet Sachar, Simon Siu-Sing Chan
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Publication number: 20080121981Abstract: A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.Type: ApplicationFiled: August 31, 2006Publication date: May 29, 2008Applicant: SPANSION LLCInventors: Hidehiko Shiraiwa, YouSeok Suh, Harpreet Sachar, Satoshi Torii
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Publication number: 20080083946Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.Type: ApplicationFiled: October 10, 2006Publication date: April 10, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Takayuki Maruyama, Hidehiko Shiraiwa, Kuo-Tung Chang, Lei Xue, Meng Ding, Amol Ramesh Joshi, YouSeok Suh, Harpreet Sachar
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Publication number: 20080023751Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.Type: ApplicationFiled: July 31, 2006Publication date: January 31, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Amol Ramesh Joshi, Harpreet Sachar, YouSeok Suh, Shenqing Fang, Chih-Yuh Yang, Lovejeet Singh, David H. Matsumoto, Hidehiko Shiraiwa, Kuo-Tung Chang, Scott A. Bell, Allison Holbrook, Satoshi Torii
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Publication number: 20070029601Abstract: A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.Type: ApplicationFiled: August 4, 2005Publication date: February 8, 2007Inventors: Takashi Orimoto, Joong Jeon, Hidehiko Shiraiwa, Simon Chan, Harpreet Sachar
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Publication number: 20060223278Abstract: A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.Type: ApplicationFiled: April 4, 2005Publication date: October 5, 2006Inventors: Unsoon Kim, Hiroyuki Kinoshita, Yu Sun, Krishnashree Achuthan, Christopher Raeder, Christopher Foster, Harpreet Sachar, Kashmir Sahota