Abstract: An instruction processing circuit includes an instruction decoder, with an instruction input coupled to an instruction source and a control output coupled to the control input of an execution circuit. The instruction decoder includes a predecoding circuit, multiple freezing circuits and multiple sub-decoding circuits. The predecoding circuit has an input coupled to the instruction input and outputs coupled to control inputs of the freezing circuits, which feed the respective parallel sub-decoding circuits. The predecoding circuit detects to which type of instruction a supplied instruction belongs, and controls, dependent on the detected type, to which of the sub-decoding circuits instruction information derived from the supplied instruction will be passed and to which of the sub-decoding circuits supply of instruction information derived from a previously supplied instruction will be frozen.

Abstract: A digital signal processing integrated circuit contains an array of interconnected and programmed or programmable digital signal processors (10). Configurable multiplexing circuits (12), are placed between IO connections (11a,b) and the IO ports of at least a plurality of the digital signal processors (10). The multiplexing circuits (12) are configured under control of configuration data, so that the multiplexing circuit (12) give the effect of accessing the IO connection only to IO signals from the IO port or ports of one or ones of the respective plurality of digital signal processors (10) that are selected by the configuration data. Preferably, each digital signal processor (10) has its IO part coupled in common to a plurality of the multiplexing circuits (12) separately from the other digital signal processing circuits.