Abstract: A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.

Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Abstract: A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.

Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Abstract: A method and system are described in a logic simulator machine for overriding a value of a net during execution of a test routine. A model of a logic design to be simulated is built utilizing the logic simulator machine. The logic design includes multiple nets. One of the nets whose actual value may be overridden is selected. A multiplexer is inserted into the model. The multiplexer receives as its inputs the actual value of the selected net, a control bit, and an override value bit. An override value is input into the multiplexer using the override value bit. The multiplexer outputs a current value of the selected net. The current value is thus propagated to other nets. The override value is propagated as the current value of the net instead of the net's actual value throughout execution of the test routine when the multiplexer control bit is set.

Abstract: A method and system are described in a logic simulator machine for efficiently creating a trace of an array which includes a plurality of storage locations. The logic simulator machine executes a test routine. Prior to executing the test routine, an initial copy of all data included within each of the storage locations of the array is stored as a first trace of the array. During execution of a first cycle the test routine, all of the write control inputs into the array are read to identify ones of the storage locations which were modified during the execution of the first cycle. A new trace of the array is generated which includes a copy of all of the data of the first trace. In addition, only those ones of the storage locations in the first trace which were modified during the first cycle are updated. A trace is thus generated by updating only those ones of the storage locations which were modified during execution of a cycle of the test routine.

Abstract: A method and system are described for efficiently overriding a value of a net in an array during execution of a test routine. The logic simulator machine is simulating a logic design which includes the array and multiple nets. A current value of the net is set equal to an override value. A normal update to the array is permitted to occur during execution of a single cycle of the test routine. A determination is then made regarding whether the override value is still stored in the array for the particular net. If the override value is not still stored in the array for this net, normal updates to the array are prohibited during a single cycle of the test routine. During this cycle of the test routine, the override value is then again stored in the net as the current value of the net. This override value is thus made available to be read during this cycle of the test routine while writes to the array are disabled.

Abstract: A method and system are described for efficiently overriding a value of a net in an array during execution of a test routine. The logic simulator machine is simulating a logic design which includes the array and multiple nets. A current value of the net is set equal to an override value. A normal update to the array is permitted to occur during execution of a single cycle of the test routine. A determination is then made regarding whether the override value is still stored in the array for the particular net. If the override value is not still stored in the array for this net, normal updates to the array are prohibited during a single cycle of the test routine. During this cycle of the test routine, the override value is then again stored in the net as the current value of the net. This override value is thus made available to be read during this cycle of the test routine while writes to the array are disabled.

Abstract: A method and system are described in a logic simulator machine for overriding a value of a net during execution of a test routine. A model of a logic design to be simulated is built utilizing the logic simulator machine. The logic design includes multiple nets. One of the nets whose actual value may be overridden is selected. A multiplexer is inserted into the model. The multiplexer receives as its inputs the actual value of the selected net, a control bit, and an override value bit. An override value is input into the multiplexer using the override value bit. The multiplexer outputs a current value of the selected net. The current value is thus propagated to other nets. The override value is propagated as the current value of the net instead of the net's actual value throughout execution of the test routine when the multiplexer control bit is set.

Abstract: A method and system are described in a logic simulator machine for efficiently creating a trace of an array which includes a plurality of storage locations. The logic simulator machine executes a test routine. Prior to executing the test routine, an initial copy of all data included within each of the storage locations of the array is stored as a first trace of the array. During execution of a first cycle the test routine, all of the write control inputs into the array are read to identify ones of the storage locations which were modified during the execution of the first cycle. A new trace of the array is generated which includes a copy of all of the data of the first trace. In addition, only those ones of the storage locations in the first trace which were modified during the first cycle are updated. A trace is thus generated by updating only those ones of the storage locations which were modified during execution of a cycle of the test routine.

Abstract: A system and method for managing service requests from peripherals connected to a personal computer or workstation by operating both in an interrupt mode and a polling mode, with selective transition therebetween. In one practice of the invention, peripheral device service requests are first managed on an interrupt basis, then transition to a polling mode when the interrupt rate exceeds a rate threshold, and subsequently revert back to the interrupt mode when the rate again decreases below a threshold. The transition is dynamic and situation adjustable by parameter selection both as to the number of service requests and as to the time interval used to initiate transition between the interrupt and polling modes.

Abstract: A data processing system including a processor that executes a plurality of instructions including at least one instruction that requires an external operation to be performed. The processor provides information for this external operation instruction to an external device and continues to execute instructions that do not require the results from this external operation. The external device receives the information from the processor, performs the external operation and provides the results to the processor. A further aspect of this data processing system is an interface that is interconnected between the processor and the external device. The processor provides the external operation information to the interface. The interface in turn provides the information to the external device and concurrently accesses data from the memory that will be required by the external device for performing the external operation.

Abstract: A data processing system including several devices connected to an asynchronous communications bus for communications between these devices. The communications bus includes a protocol that requires only a single device to regulate communication between devices at any one time. This regulating device is termed the bus master and the remaining devices are termed slaves. This protocol provides the capability for a slave device to indicate to the bus master that a new bus master is to be designated for a temporary communication. This communication with a different bus master then occurs during the communication of the designated bus master.