Abstract: A semiconductor device having a planar integrated circuit interconnect and process of fabrication. The planar integrated circuit comprises a substrate having a first line wire formed in the substrate, a dielectric layer formed on the substrate, a second line wire formed in the dielectric layer, a contact via formed within the dielectric layer extending through the dielectric layer from the second line wire to the first line wire, and a dummy via which extends into the dielectric layer and is filled with a low dielectric material.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A method of forming a wiring pattern in a device comprises forming an array of grooves in a mask, forming first spacers adjacent vertical walls of the grooves, removing the mask, forming second spacers adjacent the first spacers, and filling areas between the first spacers and areas between the second spacers with a material to form the wiring pattern.

Abstract: A semiconductor device having a planar integrated circuit interconnect and process of fabrication. The planar integrated circuit comprises a substrate having a first line wire formed in the substrate, a dielectric layer formed on the substrate, a second line wire formed in the dielectric layer, a contact via formed within the dielectric layer extending through the dielectric layer from the second line wire to the first line wire, and a dummy via which extends into the dielectric layer and is filled with a low dielectric material.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A semiconductor device having a planar integrated circuit interconnect and process of fabrication. The planar integrated circuit comprises a substrate having a first line wire formed in the substrate, a dielectric layer formed on the substrate, a second line wire formed in the dielectric layer, a contact via formed within the dielectric layer extending through the dielectric layer from the second line wire to the first line wire, and a dummy via which extends into the dielectric layer and is filled with a low dielectric material.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A method of forming a wiring pattern in a device comprises forming an array of grooves in a mask, forming first spacers adjacent vertical walls of the grooves, removing the mask, forming second spacers adjacent the first spacers, and filling areas between the first spacers and areas between the second spacers with a material to form the wiring pattern.

Abstract: A phased array (20) and method for constructing the same are disclosed. The phased array (20) includes a superstructure (22) with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) and cooperates with the cavities (40) to form cavity style filters therebetween and to form a box-beam type superstructure. Ideally, the superstructure (22) is self supporting. Electronic modules (32) and amplifiers (33) are mounted to the superstructure (22). The method includes machining a block of material to form a webbed superstructure with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) over the cavities (40) to form cavity style filters. Amplifiers (32) and antenna elements (30) are then affixed to the superstructure (22) and cover plate (28). Ideally, the cover plate (28) is affixed to the superstructure (22) using an electrically conductive adhesive.

Abstract: A ceramic-polymer composite material such as part of a microelectronics package is formed of a ceramic mixture of aluminum nitride and boron nitride, and a low-loss polymeric material. The amount of aluminum nitride is preferably from about 50 to about 90 weight percent of the ceramic mixture, but the relative amounts of the two ceramics may be adjusted to achieve thermal expansion and thermal conductivity properties required for a particular application. A mixture of the ceramics and uncured thermosetting polymeric resin is formed, pressed into the shape of the microelectronics base and/or lid, and heated (either concurrently or subsequently) to compress the mixture and cure the polymer.

Abstract: An electronic structure is formed of alternating layers of a metal and a cured ceramic-polymer mixture. The ceramic-polymer mixture is prepared by mixing small ceramic particles into a flowable, curable polymer. The mixture is spread over a first metallic layer and, optionally, B-stage cured. Additional metallic layers and ceramic-polymer layers are added in alternating fashion. Metallic interconnects may be provided through overlying ceramic-polymer layers to a particular metallic layer. The resulting structure is heated to a moderate temperature to cure the polymer.

Abstract: A phased array (20) and method for constructing the same are disclosed. The phased array (20) includes a superstructure (22) with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) and cooperates with the cavities (40) to form cavity style filters therebetween and to form a box-beam type superstructure. Ideally, the superstructure (22) is self supporting. Electronic modules (32) and amplifiers (33) are mounted to the superstructure (22). The method includes machining a block of material to form a webbed superstructure with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) over the cavities (40) to form cavity style filters. Amplifiers (32) and antenna elements (30) are then affixed to the superstructure (22) and cover plate (28). Ideally, the cover plate (28) is affixed to the superstructure (22) using an electrically conductive adhesive.

Abstract: A CHF.sub.3 -based RIE etching process is disclosed using a nitrogen additive to provide high selectivity of SiO.sub.2 or PSG to Al.sub.2 O.sub.3, low chamfering of a photoresist mask, and low RIE lag. The process uses a pressure in the range of about 200-1,000 mTorr, and an appropriate RF bias power, selected based on the size of the substrate being etched. The substrate mounting pedestal is preferably maintained at a temperature of about 0.degree. C. Nitrogen can be provided from a nitrogen-containing molecule, or as N.sub.2. He gas can be added to the gas mixture to enhance the RIE lag-reducing effect of the nitrogen.