Patents by Inventor Harris M. Morgenstern

Harris M. Morgenstern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11726904
    Abstract: A transient input/output in progress state is established during processing of an input/output testcase by a test infrastructure in a computing environment. The method includes obtaining the input/output testcase for an object having one or more pages, and processing the input/output testcase by the test infrastructure. Processing the input/output testcase by the test infrastructure includes, for a page of the object, generating a delay in the processing of the input/output testcase for the page of the object. The delay opens a transient input/output in progress state during which one or more concurrent test operations are to reference the page of the object.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: August 15, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Harris M. Morgenstern, Charles Eugene Mari, Christopher Lee Wood, Alfred Francis Foster
  • Publication number: 20230236959
    Abstract: A transient input/output in progress state is established during processing of a testcase by a test infrastructure in a computing environment. The method includes obtaining the testcase for an object having one or more pages, and processing the testcase by the test infrastructure. Processing the testcase by the test infrastructure includes, for a page of the object, generating a delay in the processing of the testcase for the page of the object. The delay opens a transient input/output in progress state during which one or more test operations reference the page of the object.
    Type: Application
    Filed: April 5, 2023
    Publication date: July 27, 2023
    Inventors: Robert MILLER, JR., Harris M. MORGENSTERN, Charles Eugene MARI, Christopher Lee WOOD, Alfred Francis FOSTER
  • Publication number: 20230086432
    Abstract: A transient input/output in progress state is established during processing of an input/output testcase by a test infrastructure in a computing environment. The method includes obtaining the input/output testcase for an object having one or more pages, and processing the input/output testcase by the test infrastructure. Processing the input/output testcase by the test infrastructure includes, for a page of the object, generating a delay in the processing of the input/output testcase for the page of the object. The delay opens a transient input/output in progress state during which one or more concurrent test operations are to reference the page of the object.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Robert MILLER, JR., Harris M. MORGENSTERN, Charles Eugene MARI, Christopher Lee WOOD, Alfred Francis FOSTER
  • Patent number: 11321239
    Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 3, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Elpida Tzortzatos, Scott B. Compton, Steven M. Partlow
  • Publication number: 20210109863
    Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Inventors: Harris M. Morgenstern, Elpida Tzortzatos, Scott B. Compton, Steven M. Partlow
  • Patent number: 10891238
    Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Elpida Tzortzatos, Scott B. Compton, Steven M. Partlow
  • Patent number: 10884950
    Abstract: Memory management is provided which includes a page replacement process managed by a storage manager and a workload manager. The page replacement process swaps out the content associated with a frame of physical memory to an auxiliary storage in order to provide a free frame. The memory management process includes: determining that the physical memory runs out of free frames; providing priority information from the workload manager to the storage manager, the priority information indicating the priority or business relevance of a certain process; selecting one or more pages to be swapped to the auxiliary storage based on the priority information; and swapping out the contents of the one or more selected pages to the auxiliary storage.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Harris M. Morgenstern, Horst Sinram, Elpida Tzortzatos, Dieter Wellerdiek
  • Publication number: 20200409862
    Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Harris M. Morgenstern, Elpida Tzortzatos, Scott B. Compton, Steven M. Partlow
  • Patent number: 10705983
    Abstract: Embodiments are provided for implementing a transparent conversion of common virtual storage requests to storage with limited access. Embodiments include providing a storage manager configured to perform address translation for requests, providing a data address translation (DAT) structure configured to connect a higher-level DAT table to a lower-level DAT table, and creating the DAT structure based on a request from a process. Embodiments also include responsive to receiving a storage request, performing a DAT fault process based on validating user credentials associated with an entry of the higher-level DAT table corresponding to the storage request, and responsive to the validation, updating the higher-level DAT table entry to allow access to the restricted-use portion of the common virtual storage, and otherwise, returning a DAT fault for the higher-level DAT table entry.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elpida Tzortzatos, Michael Gary Spiegel, Karl David Schmitz, Steven Partlow, Harris M. Morgenstern, David Hom, Peter Fatzinger
  • Patent number: 10565114
    Abstract: Provided herein is a computer-implemented method. The computer-implemented method includes updating, by a processor, a value of a delta field of an entry of a data structure indexed for the processor. The computer-implemented method also includes comparing, by the processor, a predefined threshold for a global field corresponding to the delta field and the value of the delta field. The computer-implemented method also includes rolling, by the processor, the value of the delta field into the global field when an absolute value of the value of the delta field meets or exceeds the predefined threshold for the global field. Note that the data structure is stored in a first area of a memory in communication with the processor that is separate from a second area of the memory storing the global field.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Christopher L. Wood
  • Patent number: 10552326
    Abstract: Provided herein is a computer-implemented method. The computer-implemented method includes updating, by a processor, a value of a delta field of an entry of a data structure indexed for the processor. The computer-implemented method also includes comparing, by the processor, a predefined threshold for a global field corresponding to the delta field and the value of the delta field. The computer-implemented method also includes rolling, by the processor, the value of the delta field into the global field when an absolute value of the value of the delta field meets or exceeds the predefined threshold for the global field. Note that the data structure is stored in a first area of a memory in communication with the processor that is separate from a second area of the memory storing the global field.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Christopher L. Wood
  • Patent number: 10372352
    Abstract: A memory system is configured for access by a plurality of computer processing units. An address lock bit is configured in a translation table of the memory system. The address lock supports both address lock shared and address lock exclusive functions. A storage manager of an operating system configured to obtain exclusive access to an entry in a DAT table either by obtaining an address space lock exclusive or obtaining an address space lock shared, and setting a lock bit in a DAT entry.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles E. Mari, Harris M. Morgenstern, Thomas F. Rankin, Peter J. Relson, Elpida Tzortzatos
  • Patent number: 10168960
    Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Harris M. Morgenstern, James H. Mulder, Elpida Tzortzatos, Dieter Wellerdiek
  • Publication number: 20180341590
    Abstract: Provided herein is a computer-implemented method. The computer-implemented method includes updating, by a processor, a value of a delta field of an entry of a data structure indexed for the processor. The computer-implemented method also includes comparing, by the processor, a predefined threshold for a global field corresponding to the delta field and the value of the delta field. The computer-implemented method also includes rolling, by the processor, the value of the delta field into the global field when an absolute value of the value of the delta field meets or exceeds the predefined threshold for the global field. Note that the data structure is stored in a first area of a memory in communication with the processor that is separate from a second area of the memory storing the global field.
    Type: Application
    Filed: November 13, 2017
    Publication date: November 29, 2018
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Christopher L. Wood
  • Publication number: 20180341589
    Abstract: Provided herein is a computer-implemented method. The computer-implemented method includes updating, by a processor, a value of a delta field of an entry of a data structure indexed for the processor. The computer-implemented method also includes comparing, by the processor, a predefined threshold for a global field corresponding to the delta field and the value of the delta field. The computer-implemented method also includes rolling, by the processor, the value of the delta field into the global field when an absolute value of the value of the delta field meets or exceeds the predefined threshold for the global field. Note that the data structure is stored in a first area of a memory in communication with the processor that is separate from a second area of the memory storing the global field.
    Type: Application
    Filed: May 23, 2017
    Publication date: November 29, 2018
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Christopher L. Wood
  • Publication number: 20180314557
    Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.
    Type: Application
    Filed: September 4, 2015
    Publication date: November 1, 2018
    Inventors: David Hom, Charles E. Mari, Robert J. Miller, JR., Harris M. Morgenstern, Elpida Tzortzatos
  • Patent number: 10114853
    Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Charles E. Mari, Robert J. Miller, Jr., Harris M. Morgenstern, Elpida Tzortzatos
  • Patent number: 10108466
    Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Charles E. Mari, Robert Miller, Jr., Harris M. Morgenstern, Elpida Tzortzatos
  • Patent number: 10061518
    Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20180088868
    Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 29, 2018
    Inventors: ROBERT MILLER, JR., HARRIS M. MORGENSTERN, JAMES H. MULDER, ELPIDA TZORTZATOS, DIETER WELLERDIEK