Abstract: Systems, structures, packages, circuits, and methods provide IC packages with laminated substrates configured for use with or coupling to a transformer package or assembly. IC packages can include a substrate having an encapsulant presenting an encapsulating volume for encapsulation of one or more IC die. The encapsulating volume can be configured below, at, or above a main surface of the substrate, with the packages including receiving/mounting structures to accommodate coupling of a transformer assembly. The packages and modules may include various types of circuits; in some examples, chips, chip packages, or modules may include a gate driver or other high voltage circuit.

Abstract: A voltage-isolated transformer and integrated circuit package includes a substrate with opposed first and second surfaces and including a plurality of conductive traces, with a recess disposed in the second surface. The plurality of conductive traces includes a first group and a second group that are galvanically separate. A magnetic core is disposed on the first surface of the substrate. The magnetic core can include a soft ferromagnetic material. First and second coils are configured about the magnetic core and connected to the first and second groups of conductive traces, respectively, with the first and second coils and magnetic core being configured as a transformer. First and second integrated circuit die are disposed in the recess on the second surface. A dam is disposed on the first surface of the substrate and surrounding the magnetic core. An encapsulant disposed in the dam and encapsulating the magnetic core.

Abstract: Systems, structures, packages, circuits, and methods provide leadless transformer packages for galvanic isolation. An example leadless transformer includes a substrate including opposed first and second surfaces and a plurality of conductive traces. The plurality of conductive traces includes a first group and a second group that are galvanically separate. The first group includes a plurality of exposed portions that are exposed at a first area of the substrate and the second group includes a plurality of exposed portions that are exposed at a second area of the substrate. A magnetic core is disposed on the substrate. First and second coils are each disposed about the magnetic core and configured for connection to the first and second groups of conductive traces, respectively. The package includes a dam disposed on the substrate and configured to surround the magnetic core, and an encapsulant is within the dam, encapsulating the magnetic core.

Abstract: Systems, structures, packages, circuits, and methods provide leadframe-based packages with integrated IC-transformer structures having a transformer providing galvanic isolation for included IC die. An example leadframe-based voltage-isolated IC package includes a leadframe substrate with first and second leadframe, a magnetic core disposed on one side of the leadframe substrate, first and second IC die disposed on the other side of the leadframe substrate, a body including molding material encapsulating the first and second IC die; first and second coils configured about the magnetic core, and a wall configured to surround the magnetic core. The packages and modules may include various types of circuits; in some examples, chip packages or modules may include a galvanically isolated gate driver or other high voltage circuit.

Abstract: According to one aspect of the present disclosure, a voltage isolated integrated circuit (IC) package configuration includes a first package comprising a transformer and a mold material enclosing the transformer to form a first package body, wherein the first package comprises a first lead set to permit electrical connection to the transformer. In some embodiments, a second package comprising a lead frame, two or more semiconductor die supported by the lead frame, and a mold material enclosing the two or more semiconductor die to form a second package body, wherein the lead frame comprises a second lead set to permit electrical connection to the two or more semiconductor die. In some embodiments, the one or more leads of the first lead set is directly electrically connected to one or more leads of the second lead set, wherein the first package and the second package are mechanically coupled together.

Abstract: Methods and apparatus for a first photodetector array die having pixels from a first end to a second end and a second photodetector array die having pixels from a first end to a second end. A readout integrated circuit (ROIC) can be electrically coupled to the first and second photodetector array die. One or more microlenses can steer light onto the photodetector arrays.

Abstract: A method of providing a sensor IC package can include applying a film to a leadframe having first and second surfaces, mounting at least one component to the film, and applying a pre-mold material to cover at least a portion of the leadframe and the passive component while leaving a first side of the leadframe exposed. The film can be removed and a die attached to the first side of the leadframe. At least one electrical connection can be formed between the die and the leadframe. The assembly of the die, the leadframe, and the pre-mold material can be encapsulated with a final mold material to provide a low profile IC package.

Abstract: A method of providing a sensor IC package can include applying a film to a leadframe having first and second surfaces, mounting at least one component to the film, and applying a pre-mold material to cover at least a portion of the leadframe and the passive component while leaving a first side of the leadframe exposed. The film can be removed and a die attached to the first side of the leadframe. At least one electrical connection can be formed between the die and the leadframe. The assembly of the die, the leadframe, and the pre-mold material can be encapsulated with a final mold material to provide a low profile IC package.

Abstract: An integrated circuit package system includes: forming a base stacking package including: fabricating a base substrate, mounting an integrated circuit on the base substrate, positioning an input/output expansion substrate, having access ports around an inner array area, over the integrated circuit, and injecting a molding compound on the base substrate, the integrated circuit, and the input/output expansion substrate; and mounting a top package on the input/output expansion substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base assembly having a cavity and a through conductor adjacent to the cavity; connecting a first device to the base assembly with the first device within the cavity; connecting a second device to the base assembly with the second device within the cavity; and connecting an interposer substrate having an exposed external side over the through conductor with the exposed external side facing away from the through conductor and exposed to ambient.

Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.

Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.

Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base assembly having a cavity and a through conductor adjacent to the cavity; connecting a first device to the base assembly with the first device within the cavity; connecting a second device to the base assembly with the second device within the cavity; and connecting an interposer substrate having an exposed external side over the through conductor with the exposed external side facing away from the through conductor and exposed to ambient.

Abstract: An integrated circuit package system includes: forming a base stacking package including: fabricating a base substrate, mounting an integrated circuit on the base substrate, positioning an input/output expansion substrate, having access ports around an inner array area, over the integrated circuit, and injecting a molding compound on the base substrate, the integrated circuit, and the input/output expansion substrate; and mounting a top package on the input/output expansion substrate.

Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.

Abstract: A light emitting chip package includes a planar substrate, an LED die mounted on the substrate, and one or more relatively wide and thick metal leads to serve as a low thermal resistance path. The substrate comprises a chip mounting area and a wire bond area on a dielectric body. The LED die is seated on the chip mounting area and electrically connected to the wire bonding area. The metal leads are attached to the substrate and form terminals for external connection. At least one metal lead is connected to the chip mounting area to serve as a low thermal resistance path between the chip mounting area and an external heat sink.