Patents by Inventor Harry CHIEN

Harry CHIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055491
    Abstract: A semiconductor device includes parallel channel members, a gate structure, source/drain features, a silicide layer, and a source/drain contact. The parallel channel members are spaced apart from one another. The gate structure is wrapping around the channel members. The source/drain features are disposed besides the channel members and at opposite sides of the gate structure. The silicide layer is disposed on and in direct contact with the source/drain features. The source/drain contact is disposed on the silicide layer, wherein the source/drain contact includes a first source/drain contact and a second source/drain contact stacked on the first source/drain contact, and the second source/drain contact is separate from the silicide layer by the first source/drain contact.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hung Chu, Shuen-Shin Liang, Chung-Liang Cheng, Sung-Li Wang, Chien Chang, Harry CHIEN, Lin-Yu Huang, Min-Hsuan Lu
  • Publication number: 20240021687
    Abstract: A source/drain component is disposed over an active region and surrounded by a dielectric material. A source/drain contact is disposed over the source/drain component. The source/drain contact includes a conductive capping layer and a conductive material having a different material composition than the conductive capping layer. The conductive material has a recessed bottom surface that is in direct contact with the conductive capping layer. A source/drain via is disposed over the source/drain contact. The source/drain via and the conductive material have different material compositions. The conductive capping layer contains tungsten, the conductive material contains molybdenum, and the source/drain via contains tungsten.
    Type: Application
    Filed: March 28, 2023
    Publication date: January 18, 2024
    Inventors: Cheng-Wei Chang, Chien Chang, Kan-Ju Lin, Harry Chien, Shuen-Shin Liang, Chia-Hung Chu, Sung-Li Wang, Shahaji B. More, Yueh-Ching Pai
  • Publication number: 20230411242
    Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kan-Ju LIN, Lin-Yu HUANG, Min-Hsuan LU, Wei-Yip LOH, Hong-Mao LEE, Harry CHIEN
  • Publication number: 20230411496
    Abstract: A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 21, 2023
    Inventors: Kan-Ju LIN, Chien CHANG, Chih-Shiun CHOU, Tai Min CHANG, Yi-Ning TAI, Hong-Mao LEE, Yan-Ming TSAI, Wei-Yip LOH, Harry CHIEN, Chih-Wei CHANG, Ming-Hsing TSAI, Lin-Yu HUANG
  • Publication number: 20230402278
    Abstract: A method of forming a semiconductor device includes following operations. A substrate is provided with a gate stack thereon, an epitaxial layer therein, and a dielectric layer aside the gate stack and over the epitaxial layer. An opening is formed through the dielectric layer, and the opening exposes the epitaxial layer. A metal silicon-germanide layer is formed on the epitaxial layer, wherein the metal silicon-germanide layer includes a metal having a melting point of about 1700° C. or higher. A connector is formed over the metal silicon-germanide layer in the opening.
    Type: Application
    Filed: June 12, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Ming Tsai, Wei-Yip Loh, Harry CHIEN, Chih-Shiun Chou, Hong-Mao Lee, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20230402366
    Abstract: A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 14, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Kuan-Kan HU, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN
  • Publication number: 20230395504
    Abstract: Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu Pei Chen, Chia-Hao Chang, Shin-Yi Yang, Chia-Hung Chu, Po-Chin Chang, Shuen-Shin Liang, Chun-Hung Liao, Yuting Cheng, Hung-Yi Huang, Harry Chien, Pinyen Lin, Sung-Li Wang
  • Publication number: 20230395429
    Abstract: Depositing a seed layer after formation of the MD in order to reduce or prevent epitaxial growth of the seed layer toward the MD. For example, the seed layer may be deposited using CVD and conformal dry etching. In some implementations, the seed layer may be formed of ruthenium (Ru), molybdenum (Mo), or tungsten (W). Accordingly, the seed layer helps reduce or prevent seam formation in the VG, which reduces resistance of the VG by allowing for bottom-up metal growth. Additionally, current leakage from the VG to the MD is reduced or even prevented. As a result, device performance and efficiency are increased and breakdown voltage of the gate structure is also increased. Additionally, because electrical shorts are less likely, yield is increased, which conserves power, raw materials, and processing resources that otherwise would have been consumed during manufacture.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventors: Kan-Ju LIN, Hao-Heng LIU, Chien CHANG, Hung-Yi HUANG, Harry CHIEN
  • Publication number: 20230299168
    Abstract: A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan HU, Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Ken-Yu CHANG, Wei-Yip LOH, Hung-Yi HUANG, Harry CHIEN, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN, Tzu-Pei CHEN, Yuting CHENG
  • Publication number: 20230282729
    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.
    Type: Application
    Filed: May 9, 2022
    Publication date: September 7, 2023
    Inventors: Hsin-Yi Lee, Chun-Da Liao, Cheng-Lung Hung, Yan-Ming Tsai, Harry Chien, Huang-Lin Chao, Weng Chang, Chih-Wei Chang, Ming-Hsing Tsai, Chi On Chui
  • Publication number: 20230253308
    Abstract: A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Yuting CHENG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Pinyen LIN, Sung-Li WANG, Sheng-Tsung WANG, Lin-Yu HUANG, Shao-An WANG, Harry CHIEN
  • Publication number: 20230230916
    Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN