Abstract: A processor is able to re-encode a normal value of a first floating point format to a normalized floating point format, and re-encode a subnormal value of the first floating point format to the normalized floating point format. A subset of the exponent bits of the exponent field of a normalized floating point format is used to encode a predetermined indication of being an exceptional value, wherein a combination of bit values used to encode this predetermined indication does not occur within a range of the exponent field of the normalized floating point format used to represent any possible non-exceptional, normal and subnormal values.

Abstract: A processor can re-encode from an unnormalized wider floating point format to a normalized wider floating point format, and re-encode from an unnormalized narrower floating point format to a normalized narrower floating point format. According to the disclosure, when performing a wider-format sign injection operation on a NaN-boxed value of the normalized narrower floating point format held in a source register of a set of normalized-format registers, a bit manipulation is performed on a bit in the respective source register at a most-significant bit-position of the normalized wider floating point format. When de-normalizing the NaN-boxed value of the normalized narrower floating point format from the respective source register, the bit at the most-significant bit-position of the normalized wider floating point format is ignored in detecting NaN-boxing.