Abstract: A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.

Abstract: An interposer structure and a method of interconnecting first and second semiconductor dies are provided. A splice interposer is attached to a top surface of a substrate through a first plurality of pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through a second plurality of pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through a third plurality of pillars formed on the bottom surface of the first semiconductor. The height of the second plurality of pillars is greater than the height of the third plurality of pillars. The second semiconductor die is attached to the top surface of the splice interposer through a fourth plurality of pillars formed on a bottom surface of the second semiconductor die.

Abstract: A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through second pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through third pillars formed on the bottom surface of the first semiconductor. The second semiconductor die is attached to the top surface of the splice interposer through fourth pillars formed on a bottom surface of the second semiconductor die. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.

Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.

Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.

Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.

Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.

Abstract: A structure. The structure includes a layered configuration including a copper layer, a first layer, and a second layer. The first and second layers are disposed on opposite sides of the copper layer and are in direct mechanical contact with the copper layer. The first and second layers each include a same alloy of nickel and a metal consisting of cobalt, iron, copper, manganese, or molybdenum. A first region in the first layer extends completely through the first layer. A second region in the second layer extends completely through the second layer. A third region in the first layer extends completely through the first layer. The third region does not extend into any portion of the second layer. The first, second region, and third regions each include a photoresist or an opening such that photoresist or opening extends completely through the first, second, and first layer, respectively.

Abstract: A method for mounting a film, used to fabricate a mask for use in screening an electronic device, to a common carrier frame. The common carrier frame has an outer edge along an outer periphery and an opening in a central portion of the frame. The method includes applying external pressure to the frame outer edge to compress the frame inward and reduce the opening, securing a film to the frame, the film covering the frame opening, and releasing the pressure on the frame to expand the opening and place the film in tension.

Abstract: A method for mounting a film, used to fabricate a mask for use in screening an electronic device, to a common carrier frame. The common carrier frame has an outer edge along an outer periphery and an opening in a central portion of the frame. The method includes applying external pressure to the frame outer edge to compress the frame inward and reduce the opening, securing a film to the frame, the film covering the frame opening, and releasing the pressure on the frame to expand the opening and place the film in tension.

Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.

Abstract: A structure and associated methods of formation. The structure includes a layered configuration comprising a copper layer, a first layer, and a second layer. The copper layer consists essentially of copper. The first and second layers are disposed on opposite sides of the copper layer and are in direct mechanical contact with the copper layer. The first and second layers each consist essentially of a same alloy of nickel and cobalt having a weight percent concentration of cobalt in a range of 3% to 21%. A through hole in the layered configuration extends completely through the first layer, the copper layer, and the second layer, wherein a first opening in the layered configuration extends completely through the first layer and does not extend into any portion of the second layer.

Abstract: A copper core used in electroformed metal (EFM) masks is replaced with a copper/molybdenum/copper clad core (Cu/Mo/Cu). The copper cladding on the molybdenum enhances adhesion of electroplated nickel. The nickel is electro-deposited through a patterned resist template onto the copper clad molybdenum surface. The copper and molybdenum are etched by selective etchants that do not attack other non-etched layers, leaving a patterned nickel stencil on a high-strength supporting base.

Abstract: A method for mounting a film, used to fabricate a mask for use in screening an electronic device, to a common carrier frame. The common carrier frame has an outer edge along an outer periphery and an opening in a central portion of the frame. The method includes applying external pressure to the frame outer edge to compress the frame inward and reduce the opening, securing a film to the frame, the film covering the frame opening, and releasing the pressure on the frame to expand the opening and place the film in tension.