Abstract: An SOI wafer includes a substrate, and an insulating intermediate layer and a surface layer successively thereon. At least one laterally limited suicide area is formed in and/or on the surface layer. Then an oxide layer is provided on the surface layer of the SOI wafer and/or on a second silicon wafer, before the two wafers are bonded to each other along the oxide layer. The substrate and the insulating intermediate layer are removed to leave a bonded multi-layered wafer. At least one device component is fabricated in and/or on the surface layer to include the silicide area as a functional element of the device component. Different types of components, e.g. MOS and bipolar transistors, can be fabricated together on the same wafer, and HF characteristics are improved by the low ohmic suicide area(s).

Abstract: A manufactured multi-layered silicon wafer with a buried insulating layer and buried areas with different parameters is formed by bonding together a first wafer and a second wafer. Before the bonding, areas with modified layer parameters, which will be buried by bonding with the second wafer, are created on the surface of the first wafer, which also has an insulating intermediate layer. A further insulating layer is then applied, and the surface of the first wafer is bonded to the surface of the second wafer. The substrate layer and the insulating intermediate layer of the first wafer are subsequently removed. This eliminates the conventional thinning of the second wafer. In addition, areas with vertical gradients can be created in the layer parameters without processing the second wafer.

Abstract: In a method for manufacturing a silicon wafer with an insulating intermediate layer, the surface of a first wafer, which has an insulating intermediate layer, is bonded to the surface of a second wafer, and then the substrate layer and the insulating intermediate layer of the fist wafer are removed. The new silicon surface created in this manner has a high layer quality which is achieved at a low cost.

Abstract: With the previously known methods for manufacturing a silicon wafer with an insulating intermediate layer, especially in the case of a thicker silicon layer lying upon the insulating intermediate layer, great expenditure is required in order to create a layer with the quality and surface required for producing integrated circuits.

Abstract: In the previously known methods, the buried layers, such as suicide for example, are produced on SOI wafers by thinning the wafer bonded onto the SOI wafer to the desired thickness, and then isolating the layers grown on the SOI wafer by means of a trench process.

Abstract: Method for manufacturing components on an SOI wafer.

Abstract: A method of fabricating an HBT using differential epitaxy. By using an emitter mask and an exside-inside spacer structure, a self-aligned fabrication of an emitter contact and a base contact is carried out. The emitter contact layer is made from amorphous silicon. Since the entire process sequence is very temperature-stable and can be carried out at lower implantation energies than conventional methods, HBT's having a high layer quality can be fabricated by the method of the invention which is suitable for mass production and with which high oscillation frequencies can be accomplished.

Abstract: A process for preparing a bipolar transistor for very high frequencies is described, which is especially advantageous for the preparation of heterobipolar transistors and leads to components with low parasitic capacities and low base lead resistance. The process includes forming a structured first layer with collector zone and insulation areas surrounding the collector zone on a monocrystalline lead layer. A series of monocrystalline transistor layers are grown on the first layer over the collector zone by differential epitaxy and a series of polycrystalline layers is grown at the same time over the insulation areas. A series of polycrystalline layers is designed as a base lead.

Abstract: Manufacture of a semiconductor array of integrated silicon-germanium heterobipolar transistors having a silicon collector layer, a silicon-germanium base layer, a silicon emitter layer and a silicon emitter contact layer includes depositing in a single uninterrupted process and simultaneously doping the collector layer, the base layer, the emitter layer and the emitter contact layer. A base connection region is formed at the side of the base layer such that the intersection surfaces of the base/emitter/PN boundary layer and of the base/collector PN boundary layer with the surface of the semiconductor array are outside the silicon-germanium base layer. A silicon dioxide layer is formed by thermal oxidation over the entire exposed surface of the semiconductor array.