Abstract: Reliable branch predictions for real-time applications reduce both conditional branch execution time and uncertainties associated with their prediction in a computer implemented application. One method ensures that certain conditional branches are always correctly predicted, effectively converting them to jump instructions during program execution. Another method exploits the fact that some conditional branches always branch in the same direction within a task invocation, although that direction may vary across invocations. These methods improve computer processor utilization and performance.

Abstract: An apparatus and method in digital processing provides a simple and efficient way of communicating parameters from a parent thread to child thread with two step thread creation. The method comprising the steps of: allocating hardware context for the child thread; enabling the parent thread to execute other instructions wherein parent thread register writes update both parent and child architectural registers; and spawning the child thread. In essence, the parent thread sends parameters to the child by writing to the parent's registers prior to spawning of the child thread.

Abstract: A circuit and a scheme for register renaming responsive to a thread ID register, comprises: a plurality of physical registers; a plurality of architectual registers; a rename logic circuit where every write to an architectual register of the plurality of architectural registers is assigned a new physical register of the plurality of physical registers; a register map circuit containing a corresponding entry for each of the plurality of architectual registers. The register map circuit is responsive to the thread ID register such that a different physical map is selected for architectual registers of each thread, whereby the plurality of architectual registers can be greater than the plurality of physical registers.

Abstract: Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.

Abstract: Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.

Abstract: A mounting apparatus for the quick-detachable securing of a flashlight or a like target illumination device to a firearm. The mounting device includes a passage for receiving the barrel of the flashlight or the like. The passage is provided with a resilient means to press the flashlight longitudinally along approximately the same axis as the firearm's barrel in opposition to a springably-positioned latch system engaging one end of the flashlight which prevents its dislodgment upon movement of the firearm during handling or discharge, yet enabling relatively quick, one-handed release and replacement of the entire flashlight. The flashlight or the like is prevented from rotating in the passage by a groove in the interior of the passage that engages part of the flashlight body thereby indexing it so that the flashlight's controls are always in the same position and accessible to the user.

Abstract: A thresholding mechanism and method for performance monitoring of memory array access distribution times is disclosed. A data request signal sent to the memory hierarchy activates a first counter, having a first count value. A clock coupled to the first counter increments the first count value with each clock cycle, while also decrementing a decrementer having a predetermined threshold value. The first counter is deactivated by a completion signal when the data request is completed. A second counter having a second count value is incremented when the first count value is greater than the threshold value by the time the data request is complete.

Abstract: Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.