Abstract: A data memory includes a plurality of memory cells that are selectively operable during a memory read operation to generate a data signal indicative of data stored in that memory cell, and one or more sense amplifiers are connected to receive data signals from a plurality of the memory cells. An address decoder is responsive to a memory address supplied to the data memory for controlling one of said plurality of memory cells connected to each of the sense amplifiers to generate a respective data signal under the control of a first control signal. The data memory also includes circuitry for delaying the first control signal to generate a second control signal, and for energizing the one or more sense amplifiers for operation in response to the second control signal.

Abstract: A data memory includes a memory cell that operates to generate two complementary data outputs indicative of a data bit stored in the memory cell. First and second sense amplifiers set an output latch to a first output logic state in response to a first state of the complementary data output signals, and set the output latch to a second output logic state in response to a second state of the data output signals. One or the other, but not both of the sense amplifiers change state in response to the complimentary data outputs received thereby during a memory read operation.

Abstract: A data memory and a method of reading a data memory are described. Data words (Word0, Word1, Word2, Word3) are stored within the data memory within an array of memory cells arranged in columns and rows. A particular data word within a memory cell is accessed by activating a complete row (2) to output the data words within all columns of that row and then selecting the data word from the appropriate column with a data word selection multiplexer (6). An amplifier (8) is used to reduce the time taken for data signals read from the array to reach readable values. In order to save power, the amplifier is disabled during a second and subsequent successive reading operations from a row that has already been activated. Precharging of a output lines is also disabled for second and subsequent successive readings from a row.