Abstract: A Field Programmable Gate Array (FPGA) evaluation board may include a firmware/software architecture that facilitates easier prototyping of new GPS receiver designs. A single reprogrammable FPGA with an integrated soft processor and spare logic resources may be targeted to expand the GPS receiver design. The system may operate on an FPGA evaluation board with the ability to integrate easily with various types of analog/radio frequency (RF) hardware. A hardware platform with a variety of connections to a computer may be utilized to be able to read telemetry from the receiver and analyze the performance.