Patents by Inventor Harry Gee
Harry Gee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9362499Abstract: A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline.Type: GrantFiled: March 10, 2015Date of Patent: June 7, 2016Assignee: Crossbar, Inc.Inventors: Harry Gee, Sung Hyun Jo, Hagop Nazarian, Scott Brad Herner
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Publication number: 20150188051Abstract: A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline.Type: ApplicationFiled: March 10, 2015Publication date: July 2, 2015Inventors: Harry GEE, Sung Hyun JO, Hagop NAZARIAN, Scott Brad HERNER
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Patent number: 8975609Abstract: A method of forming a non-volatile memory device. A substrate is provided and a first dielectric material forms overlying the substrate. A first polysilicon material is deposited overlying the first dielectric material. A second dielectric material is deposited overlying the first polysilicon material. A second polysilicon material is deposited overlying the second dielectric material. A third dielectric material is formed overlying the second polysilicon material. The third dielectric material, the second polysilicon material, the second dielectric material, and the first polysilicon material is subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material, a third wordline and associated with a third switching device, and a fourth wordline associated with a fourth switching device from the second polysilicon material.Type: GrantFiled: April 12, 2013Date of Patent: March 10, 2015Assignee: Crossbar, Inc.Inventors: Harry Gee, Sung Hyun Jo, Hagop Nazarian, Scott Brad Herner
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Patent number: 8946667Abstract: A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first wiring structure overlies the first dielectric material. The method forms a first electrode material overlying the first wiring structure and a resistive switching material comprising overlying the first electrode material. An active metal material is formed overlying the resistive switching material. The active metal material is configured to form an active metal region in the resistive switching material upon application of a thermal energy characterized by a temperature no less than about 100 Degree Celsius. In a specific embodiment, the method forms a blocking material interposing the active metal material and the resistive switching material to inhibit formation of the active metal region in the resistive switching material during the subsequent processing steps.Type: GrantFiled: April 13, 2012Date of Patent: February 3, 2015Assignee: Crossbar, Inc.Inventors: Mark Harold Clark, Steven Maxwell, Harry Gee, Natividad Vasquez
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Publication number: 20130234092Abstract: A method of forming a non-volatile memory device. A substrate is provided and a first dielectric material forms overlying the substrate. A first polysilicon material is deposited overlying the first dielectric material. A second dielectric material is deposited overlying the first polysilicon material. A second polysilicon material is deposited overlying the second dielectric material. A third dielectric material is formed overlying the second polysilicon material. The third dielectric material, the second polysilicon material, the second dielectric material, and the first polysilicon material is subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material, a third wordline and associated with a third switching device, and a fourth wordline associated with a fourth switching device from the second polysilicon material.Type: ApplicationFiled: April 12, 2013Publication date: September 12, 2013Applicant: Crossbar, Inc.Inventors: Harry GEE, Sung Hyun JO, Hagop NAZARIAN, Scott Brad HERNER
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Patent number: 8426306Abstract: A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline.Type: GrantFiled: December 30, 2011Date of Patent: April 23, 2013Assignee: Crossbar, Inc.Inventors: Harry Gee, Sung Hyun Jo, Hagop Nazarian, Scott Brad Herner
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Patent number: 8199447Abstract: A semiconductor device is described that includes one or more electrostatic discharge (ESD) protection circuits. Each circuit comprises reverse-biased steering diodes connected in series between power rail and signal ground, a bypass Zener diode and a substrate Zener diode. The Zener diodes provide ESD protection and the steering diode cooperate with the substrate Zener diode to provide a bypass function that is substantially symmetric about the signal ground. Noise in the circuit can be shunted using internal and/or external capacitances that can be implemented as Zener diodes.Type: GrantFiled: January 4, 2010Date of Patent: June 12, 2012Assignee: Semiconductor Components Industries, LLCInventors: Harry Gee, Wenjiang Zeng, Jeffrey C. Dunnihoo
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Publication number: 20110163352Abstract: A semiconductor device is described that includes one or more electrostatic discharge (ESD) protection circuits. Each circuit comprises reverse-biased steering diodes connected in series between power rail and signal ground, a bypass Zener diode and a substrate Zener diode. The Zener diodes provide ESD protection and the steering diode cooperate with the substrate Zener diode to provide a bypass function that is substantially symmetric about the signal ground. Noise in the circuit can be shunted using internal and/or external capacitances that can be implemented as Zener diodes.Type: ApplicationFiled: January 4, 2010Publication date: July 7, 2011Applicant: California Micro DevicesInventors: Harry Gee, Wenjiang Zeng, Jeffrey C. Dunnihoo
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Publication number: 20060223261Abstract: A method for fabricating a low dynamic resistance capacitor is an integrated circuit using conventional CMOS processing steps, where in one implementation the structure provides the additional feature of a Zener diode capable of offering ESD protection.Type: ApplicationFiled: March 31, 2005Publication date: October 5, 2006Applicant: California Micro Devices CorporationInventors: John Jorgensen, Harry Gee