Patents by Inventor Harry Gomez

Harry Gomez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210210385
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Application
    Filed: March 24, 2021
    Publication date: July 8, 2021
    Inventors: Abhijit Jayant PETHE, Tahir GHANI, Mark BOHR, Clair WEBB, Harry GOMEZ, Annalisa CAPPELLANI
  • Patent number: 11004739
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Patent number: 10847631
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Publication number: 20190157411
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Inventors: Annalisa CAPPELLANI, Abhijit Jayant PETHE, Tahir GHANI, Harry GOMEZ
  • Publication number: 20190115257
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Inventors: Abhijit Jayant PETHE, Tahir GHANI, Mark BOHR, Clair WEBB, Harry GOMEZ, Annalisa CAPPELLANI
  • Patent number: 10229981
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Patent number: 10192783
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Patent number: 10026829
    Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Stephen M. Cea, Tahir Ghani, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys, Seiyon Kim, Kelin J. Kuhn, Aaron D. Lilak, Rafael Rios, Mayank Sahni
  • Patent number: 9978636
    Abstract: Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Harry Gomez
  • Publication number: 20170162676
    Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Annalisa CAPPELLANI, Stephen M. CEA, Tahir GHANI, Harry GOMEZ, Jack T. KAVALIEROS, Patrick H. KEYS, Seiyon KIM, Kelin J. KUHN, Aaron D. LILAK, Rafael RIOS, Mayank SAHNI
  • Patent number: 9608059
    Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Stephen M. Cea, Tahir Ghani, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys, Seiyon Kim, Kelin J. Kuhn, Aaron D. Lilak, Rafael Rios, Mayank Sahni
  • Publication number: 20170047416
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Publication number: 20170004998
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Application
    Filed: September 15, 2016
    Publication date: January 5, 2017
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Publication number: 20160336219
    Abstract: Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
    Type: Application
    Filed: July 25, 2016
    Publication date: November 17, 2016
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Harry Gomez
  • Patent number: 9484272
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Patent number: 9461143
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Publication number: 20160284605
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Application
    Filed: April 30, 2014
    Publication date: September 29, 2016
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Patent number: 9425212
    Abstract: Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 23, 2016
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Harry Gomez
  • Publication number: 20150318219
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Patent number: 8735869
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez