Patents by Inventor Harry H. Fujimoto

Harry H. Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040155325
    Abstract: Microelectronic packages including a microelectronic die disposed within a recess in a heat spreader and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the heat spreader to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die within the heat spreader. In another embodiment, a microelectronic die is disposed on a heat spreader which has a filler material disposed therearound and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the filler material to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die on the heat spreader.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 12, 2004
    Applicant: Intel Corporation
    Inventors: Qing Ma, Harry H. Fujimoto, Steven Towle, John E. Evert
  • Patent number: 6709898
    Abstract: Microelectronic packages including a microelectronic die disposed within a recess in a heat spreader and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the heat spreader to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die within the heat spreader. In another embodiment, a microelectronic die is disposed on a heat spreader which has a filler material disposed therearound and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the filler material to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die on the heat spreader.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: March 23, 2004
    Assignee: Intel Corporation
    Inventors: Qing Ma, Harry H. Fujimoto, Steven Towle, John E. Evert
  • Patent number: 5962196
    Abstract: Process for post exposure treatment of a latent image on a semiconductor wafer. After a deep ultraviolet (UV) photoresist has been exposed, the wafer, including the latent image in the attached photoresist, is maintained in an inert gas to protect the resist from the air atmosphere. Then the latent image is baked to stabilize the image.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: October 5, 1999
    Assignee: Intel Corporation
    Inventors: Siddhartha Das, Harry H. Fujimoto, Henry Gaw
  • Patent number: 5747879
    Abstract: An improvement in a metal stack used for interconnecting structures in an integrated circuit. The improvement comprises the entrapping in a titanium layer of nitrogen at the interface where the titanium layer contacts a bulk conductor layer such as an aluminum-copper alloy layer. The entrapped nitrogen prevents the formation of any substantial amount of titanium aluminide thereby reducing current densities and also improving the electromigration properties of the stack. As currently preferred, the nitrogen is entrapped in approximately the first 30.ANG. of the titanium layer.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: May 5, 1998
    Assignee: Intel Corporation
    Inventors: Rajiv Rastogi, Sandra J. Underwood, Harry H. Fujimoto
  • Patent number: 5540346
    Abstract: Manufacturing techniques for forming waveguide channels and devices. A trench is formed in a cladding layer through an opening in a conductive layer. The trench is then filled with an active waveguide polymer and the conductive layer is patterned such that the active waveguide polymer may be poled. Also, a trench may be isotropically etched through a cladding layer to an underlying etch stop layer. The etch stop layer is thereafter removed from within the trench region to expose a previously formed, smooth, underlying cladding layer. Finally, a waveguide formed in a cladding layer, bounded in width by an overlying barrier layer, underlies a masking layer having a gap formed therein. Within the gap, a portion of the waveguide channel along with juxtaposing sections of the barrier layer are exposed. An etch is thereafter performed to remove the portion of the waveguide polymer in the waveguide channel bounded by both the masking layer and the barrier layer.
    Type: Grant
    Filed: June 28, 1995
    Date of Patent: July 30, 1996
    Assignee: Intel Corporation
    Inventors: Harry H. Fujimoto, Siddhartha Das
  • Patent number: 5465860
    Abstract: Manufacturing techniques for forming waveguide channels and devices. A trench is formed in a cladding layer through an opening in a conductive layer. The trench is then filled with an active waveguide polymer and the conductive layer is patterned such that the active waveguide polymer may be poled. Also, a trench may be isotropically etched through a cladding layer to an underlying etch stop layer. The etch stop layer is thereafter removed from within the trench region to expose a previously formed, smooth, underlying cladding layer. Finally, a waveguide formed in a cladding layer, bounded in width by an overlying barrier layer, underlies a masking layer having a gap formed therein. Within the gap, a portion of the waveguide channel along with juxtaposing sections of the barrier layer are exposed. An etch is thereafter performed to remove the portion of the waveguide polymer in the waveguide channel bounded by both the masking layer and the barrier layer.
    Type: Grant
    Filed: July 1, 1994
    Date of Patent: November 14, 1995
    Assignee: Intel Corporation
    Inventors: Harry H. Fujimoto, Siddhartha Das
  • Patent number: 5384219
    Abstract: A phase-shifted reticle with patterns proximate each other having inverted phases for the features and phase-shifting elements, and method of fabricating the reticle. Each of the patterns and inverted patterns are structurally identical with regard to the direction of phase shift, so that any focal shift due to phase error is in the same direction for all patterns. In a preferred embodiment, the structurally identical inverted reticle is used to form an array of closely spaced contact or via openings. For a first pattern on the reticle, the feature will be the 0.degree. phase and the phase-shifting rim surrounding that feature will be the 180.degree. phase. All patterns surrounding the first pattern have phase-shifting rims of the 0.degree. phase and features of the 180.degree. phase. In this way, each pattern can form below conventional resolution features in the resist.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: January 24, 1995
    Assignee: Intel Corporation
    Inventors: Giang T. Dao, Qi De Qian, Nelson N. Tam, Eng T. Gaw, Harry H. Fujimoto
  • Patent number: 5348826
    Abstract: A phase-shifted reticle with patterns proximate each other having inverted phases for the features and phase-shifting elements, and methods of fabricating the reticle. Each of the patterns and inverted patterns are structurally identical with regard to the direction of phase shift, so that any focal shift due to phase error is in the same direction for all patterns. In a preferred embodiment, the structurally identical inverted reticle is used to form an array of closely spaced contact or via openings. For a first pattern on the reticle, the feature will be the 0.degree. phase and the phase-shifting rim surrounding that feature will be the 180.degree. phase. All patterns surrounding the first pattern have phase-shifting rims of the 0.degree. phase and features of the 180.degree. phase. In this way, each pattern can form below conventional resolution features in the resist.
    Type: Grant
    Filed: February 2, 1993
    Date of Patent: September 20, 1994
    Assignee: Intel Corporation
    Inventors: Giang T. Dao, Qi De Qian, Nelson N. Tam, Eng T. Gaw, Harry H. Fujimoto
  • Patent number: 5302477
    Abstract: A phase-shifted reticle with patterns proximate each other having inverted phases for the features and phase-shifting elements, and methods of fabricating the reticle, are disclosed. In a preferred embodiment, the inverted reticle is used to form an array of closely spaced contact or via openings. For a first pattern on the reticle, the feature will be the 0.degree. phase and the phase-shifting rim surrounding that feature will be the 180.degree. phase. All patterns surrounding the first pattern have phase-shifting rims of the 0.degree. phase and features of the 180.degree. phase. In this way, each pattern can form below conventional resolution features in the resist. Additionally, there will not be exposure of the regions between the closely spaced features since radiation transmitted through the closely spaced phase-shifting rims of the two patterns is 180.degree. out of phase.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: April 12, 1994
    Assignee: Intel Corporation
    Inventors: Giang T. Dao, Ruben A. Rodriguez, Harry H. Fujimoto