Abstract: A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

Abstract: A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.

Abstract: A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path means, and an output logic gate. The signal-path means coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

Abstract: A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.

Abstract: A bit/column latch comprising a pair of first and second cross-coupled CMOS inverters. Each inverter of the pair comprises an NMOS transistor and a PMOS transistor. The first CMOS inverter has the source of its NMOS transistor coupled to ground via a control transistor and has its output connected to the associated bit line. When low voltage data intended for the associated memory cell appears on the bit line, the control transistor is barely turned on to weaken the NMOS transistor of the first inverter. This makes it easier for the data on the bit line to turn on the NMOS transistor of the second inverter so as to switch the bit latch from storing a ‘low’ to storing a ‘high’. In other words, the data bit from the bit line is loaded into the bit latch. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch. As a result, the latch is stable when the bit line later ramps up to a high programming level.

Abstract: A bit/column latch comprising a pair of first and second cross-coupled CMOS inverters. Each inverter of the pair comprises an NMOS transistor and a PMOS transistor. The first CMOS inverter has the source of its NMOS transistor coupled to ground via a control transistor and has its output connected to the associated bit line. When low voltage data intended for the associated memory cell appears on the bit line, the control transistor is barely turned on to weaken the NMOS transistor of the first inverter. This makes it easier for the data on the bit line to turn on the NMOS transistor of the second inverter so as to switch the bit latch from storing a ‘low’ to storing a ‘high’. In other words, the data bit from the bit line is loaded into the bit latch. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch. As a result, the latch is stable when the bit line later ramps up to a high programming level.

Abstract: A programmable logic chip and configuration memory chip are mounted within a multi-chip module to form a single package. The configuration memory has a security bit which in a first state allows programming and read-back of configuration data in the memory chip via external pins of the package, and in a second state allows only erase command to be communicated to the memory chip via the external pins. The internal data transfer connection between the memory chip and programmable logic chip is enabled when the security bit is in the second state and the memory chip is in a read-back mode, allowing configuration data to be loaded into the logic chip upon power up.

Abstract: A voltage regulator circuit that receives an input signal and provides an output signal that is clamped at a specified voltage desired for an internal circuit. The disclosed voltage regulator circuit includes a plurality of subcircuits including a voltage tracking subcircuit in which the output voltage tracks the input voltage with no voltage drop when the input voltage starts to rise from zero volts. If the input voltage increases to a desired voltage level for the internal circuit, the voltage tracking subcircuit clamps the output voltage to remain at that voltage. If the input voltage further increases to a higher voltage, the voltage tracking subcircuit is disabled and one of a plurality of voltage maintaining subcircuit takes control so that the output voltage remains at the desired voltage for the internal circuit.