Patents by Inventor Harry Hongyue Liu
Harry Hongyue Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10684778Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.Type: GrantFiled: September 4, 2015Date of Patent: June 16, 2020Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Yuan Yan, Harry Hongyue Liu
-
Publication number: 20150378607Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.Type: ApplicationFiled: September 4, 2015Publication date: December 31, 2015Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Yuan Yan, Harry Hongyue Liu
-
Patent number: 9128821Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.Type: GrantFiled: June 11, 2009Date of Patent: September 8, 2015Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Yuan Yan, Harry Hongyue Liu
-
Patent number: 8966181Abstract: Various embodiments of the present invention are generally directed to an apparatus and method for non-volatile caching of data in a memory hierarchy of a data storage device. In accordance with some embodiments, a pipeline memory structure is provided to store data for use by a controller. The pipeline has a plurality of hierarchical cache levels each with an associated non-volatile filter cache and a non-volatile victim cache. Data retrieved from each cache level are respectively promoted to the associated non-volatile filter cache. Data replaced in each cache level are respectively demoted to the associated non-volatile victim cache.Type: GrantFiled: December 11, 2008Date of Patent: February 24, 2015Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Alan Xuguang Wang
-
Patent number: 8934281Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.Type: GrantFiled: October 17, 2011Date of Patent: January 13, 2015Assignee: Seagate Technology LLCInventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
-
Patent number: 8582347Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N?1 memory cells of the plurality via the common floating source line.Type: GrantFiled: January 28, 2013Date of Patent: November 12, 2013Assignee: Seagate Technology LLCInventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
-
Patent number: 8553454Abstract: Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.Type: GrantFiled: February 20, 2012Date of Patent: October 8, 2013Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
-
Patent number: 8363449Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N?1 memory cells of the plurality via the common floating source line.Type: GrantFiled: August 10, 2011Date of Patent: January 29, 2013Assignee: Seagate Technology LLCInventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
-
Patent number: 8363450Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.Type: GrantFiled: October 24, 2011Date of Patent: January 29, 2013Assignee: Seagate Technology LLCInventors: Chulmin Jung, Yong Lu, Insik Jin, YoungPil Kim, Harry Hongyue Liu
-
Patent number: 8363442Abstract: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.Type: GrantFiled: October 13, 2010Date of Patent: January 29, 2013Assignee: Seagate Technology LLCInventors: Harry Hongyue Liu, Haiwen Xi, Antoine Khoueir, Song Xue
-
Patent number: 8289759Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.Type: GrantFiled: April 21, 2011Date of Patent: October 16, 2012Assignee: Seagate Technology LLCInventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar V. Dimitrov, Wei Tian, Brian S. Lee
-
Patent number: 8289752Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.Type: GrantFiled: January 19, 2012Date of Patent: October 16, 2012Assignee: Seagate Technology LLCInventors: Yong Lu, Harry Hongyue Liu
-
Patent number: 8289804Abstract: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N?1 output lines.Type: GrantFiled: May 4, 2011Date of Patent: October 16, 2012Assignee: Seagate Technology LLCInventors: Chulmin Jung, Dadi Setiadi, YoungPil Kim, Harry Hongyue Liu, Hyung-Kyu Lee
-
Patent number: 8203862Abstract: An apparatus and associated method for generating a reference voltage with dummy resistive sense element regions. A first resistance distribution is obtained for a first dummy region of resistance sense elements and a second resistance distribution is obtained for a second dummy region of resistive sense elements. A user resistive sense element from a user region is assigned to a selected resistive sense element of one of the first or second dummy regions in relation to the first and second resistance distributions.Type: GrantFiled: July 13, 2009Date of Patent: June 19, 2012Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Yuan Yan, Harry Hongyue Liu
-
Patent number: 8203894Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.Type: GrantFiled: April 6, 2011Date of Patent: June 19, 2012Assignee: Seagate Technology LLCInventors: Chulmin Jung, Insik Jin, YoungPil Kim, Yong Lu, Harry Hongyue Liu, Andrew John Carter
-
Patent number: 8203893Abstract: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.Type: GrantFiled: August 16, 2011Date of Patent: June 19, 2012Assignee: Seagate Technology LLCInventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Henry Huang, Ran Wang
-
Patent number: 8203899Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.Type: GrantFiled: November 15, 2010Date of Patent: June 19, 2012Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Ran Wang, Harry Hongyue Liu
-
Publication number: 20120147665Abstract: Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.Type: ApplicationFiled: February 20, 2012Publication date: June 14, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
-
Patent number: 8194437Abstract: Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.Type: GrantFiled: January 13, 2009Date of Patent: June 5, 2012Assignee: Seagate Technology LLCInventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
-
Publication number: 20120120713Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.Type: ApplicationFiled: January 19, 2012Publication date: May 17, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Yong Lu, Harry Hongyue Liu