Patents by Inventor Harry Huy Dang
Harry Huy Dang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10615785Abstract: Duty cycle correction circuits are provided that include a serial combination of a first inverter and a second inverter for inverting an input clock signal into an output clock signal having a corrected duty cycle. The duty cycle correction circuits also include a serial combination of a third inverter and a fourth inverter for inverting a complement input clock signal into a complement output clock signal having a corrected duty cycle.Type: GrantFiled: March 21, 2019Date of Patent: April 7, 2020Assignee: QUALCOMM IncorporatedInventors: Shih-Wei Chou, Ying Duan, Abhay Dixit, Harry Huy Dang, Thomas Clark Bryan
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Patent number: 10033519Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.Type: GrantFiled: November 10, 2016Date of Patent: July 24, 2018Assignee: QUALCOMM IncorporatedInventors: Ying Duan, Yasser Ahmed, Abhay Dixit, Harry Huy Dang, Jing Wu
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Publication number: 20180131503Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.Type: ApplicationFiled: November 10, 2016Publication date: May 10, 2018Inventors: Ying Duan, Yasser Ahmed, Abhay Dixit, Harry Huy Dang, Jing Wu
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Patent number: 9401731Abstract: Aspects disclosed in the detailed description include skew control for three-phase communication. A three-phase communication involves three signal branches. A signal skew may occur when one signal branch is being coupled to a common mode voltage while another signal branch is being decoupled from the common mode voltage. In this regard, in one aspect, an impedance mismatch is introduced in the signal branch being coupled to the common mode voltage to help shift a rightmost crossing of the signal skew leftward. In another aspect, a current source or a current sink is coupled to the signal branch being decoupled from the common mode voltage to help shift a leftmost crossing of the signal skew rightward. By shifting the rightmost crossing leftward and the leftmost crossing rightward, it is possible to reduce the signal skew, thus leading to reduced jitter and improved data integrity in the three-phase communication.Type: GrantFiled: May 27, 2015Date of Patent: July 26, 2016Assignee: QUALCOMM IncorporatedInventors: Ying Duan, Harry Huy Dang, Chulkyu Lee
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Publication number: 20150381218Abstract: Aspects disclosed in the detailed description include skew control for three-phase communication. A three-phase communication involves three signal branches. A signal skew may occur when one signal branch is being coupled to a common mode voltage while another signal branch is being decoupled from the common mode voltage. In this regard, in one aspect, an impedance mismatch is introduced in the signal branch being coupled to the common mode voltage to help shift a rightmost crossing of the signal skew leftward. In another aspect, a current source or a current sink is coupled to the signal branch being decoupled from the common mode voltage to help shift a leftmost crossing of the signal skew rightward. By shifting the rightmost crossing leftward and the leftmost crossing rightward, it is possible to reduce the signal skew, thus leading to reduced jitter and improved data integrity in the three-phase communication.Type: ApplicationFiled: May 27, 2015Publication date: December 31, 2015Inventors: Ying Duan, Harry Huy Dang, Chulkyu Lee
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Patent number: 6876263Abstract: A voltage-controlled oscillator (“VCO”) structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.Type: GrantFiled: March 5, 2003Date of Patent: April 5, 2005Assignee: Applied Micro Circuits CorporationInventors: Wei Li, Thomas Clark Bryan, Harry Huy Dang, Mehmet Mustafa Eker
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Patent number: 6720818Abstract: An amplitude of a differential output signal at a differential multiplexer is maximized by presenting, in response to a differential selection signal, a high impedance to each output port of each differential transistor of a non-selected differential transistor pair. A differential input signal is received at each differential transistor pair. Each transistor of each differential transistor pair is connected to a current source through an independent selection transistor. In response to the differential selection signal, each of the selection transistors is placed in an off state resulting in a high impedance between the output ports of the transistors of the non-selected differential transistor pair.Type: GrantFiled: November 8, 2002Date of Patent: April 13, 2004Assignee: Applied Micro Circuits CorporationInventors: Zhixiang Jason Liu, Shuyu Lei, Harry Huy Dang, Thomas Clark Bryan
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Patent number: 6552582Abstract: A source follower circuit for low voltage differential signaling (LVDS) has a low power consumption, low noise, and the ability to drive a highly capacitive load at an output port of an integrated circuit (IC). The source follower circuit includes a first p-channel transistor having a drain coupled to a supply voltage and a gate coupled to a first input; a second p-channel transistor having a drain coupled to the supply voltage and a gate coupled to a second input which is complementary to the first input; a third p-channel transistor having a gate coupled to the second input, a source coupled to ground, and a drain coupled to a source of the first p-channel transistor which forms a first output; and a fourth p-channel transistor having a source coupled to the ground and a drain coupled to a source of the second p-channel transistor which forms a second output which is complementary to the first output.Type: GrantFiled: September 27, 2001Date of Patent: April 22, 2003Assignee: Applied Micro Circuits CorporationInventors: Thomas Clark Bryan, Harry Huy Dang
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Patent number: 6169421Abstract: A CMOS buffer for interfacing TTL-standard signals and capable of driving a high capacitance load such as a transmission line with low switching noise and low power consumption. The CMOS buffer includes two CMOS branch circuits that control the operation of a CMOS output device. Each branch circuit includes a first delay and a second delay greater than the first delay. The CMOS output device includes a complementary pair of MOS transistors. The first MOS transistor of the CMOS output device is operated by the first branch circuit in response to a signal that is delayed by the first or the second delay. The second MOS transistor of the CMOS output device is operated by the second branch circuit in response to delay of the signal by the second or the first delay.Type: GrantFiled: May 3, 1999Date of Patent: January 2, 2001Assignee: Applied Micro Circuits CorporationInventors: Thomas Clark Bryan, Harry Huy Dang
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Patent number: 5955924Abstract: A differential cMOS push-pull buffer includes a pair of push-pull sections, a cMOS current source transistor connected to the push-pull sections for providing current thereto, and two cMOS trickle current transistors, each connected to an output node of a respective push-pull section for conducting a trickle current at the output node. In each push-pull section a trickle current enhances the speed of operation, thereby maintaining desirable attributes in output waveforms.Type: GrantFiled: April 21, 1998Date of Patent: September 21, 1999Assignee: Applied Micro Circuits CorporationInventors: Thomas Clark Bryan, Harry Huy Dang