Abstract: A method of testing an integrated circuit device that includes components of first and second types, where the components of the second type consume power when clocked even when not active, includes gating off the clock signal to prevent clock signals from reaching the components of the second type, and applying test inputs to the components of the first type. Gating off the clock signals to the components of the second type may include preventing the clock signals from reaching individual components of the second type, or preventing the clock signals from reaching each clock tree branch that contains only components of the second type, or, when a clock tree serving the components of the second type supplies clock signals only to the components of the second type, preventing the clock signals from reaching the clock tree.

Abstract: System, method, and program product analyze netlists for related electrical circuit designs by comparing predefined physical characteristics between the netlists. A baseline reference score is generated for one of the netlists and a normalized score is generated for the other netlist. The baseline reference score and the normalized score are used to generate a similarity score that is displayed on a display monitor. Preferably, the similarity score is displayed as a percentage.

Abstract: System, method, and program product analyze netlists for related electrical circuit designs by comparing predefined physical characteristics between the netlists. A baseline reference score is generated for one of the netlists and a normalized score is generated for the other netlist. The baseline reference score and the normalized score are used to generate a similarity score that is displayed on a display monitor. Preferably, the similarity score is displayed as a percentage.

Abstract: An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions.

Abstract: Exemplary embodiments of the present invention comprise a method for the support of a JTAG interface for the testing of connectivity between integrated circuits. The method comprises delivering output from a JTAG register to a primary register, delivering a JTAG control signal to the primary register and a clock signal gating control logic, delivering output from the primary register and a secondary register to a multiplexer, delivering clock signal output from the clock signal gating control logic to the multiplexer, wherein the clock signal is delivered is a constant and known value, and delivering the output from the multiplexer to an I/O driver.

Abstract: An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. Each of the one or more voltage islands comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions. The redundancy initialization component is configured to initialize each memory using redundancy and associated repair register with repair data.

Abstract: Exemplary embodiments of the present invention comprise a method for the support of a JTAG interface for the testing of connectivity between integrated circuits. The method comprises delivering output from a JTAG register to a primary register, delivering a JTAG control signal to the primary register and a clock signal gating control logic, delivering output from the primary register and a secondary register to a multiplexer, delivering clock signal output from the clock signal gating control logic to the multiplexer, wherein the clock signal is delivered is a constant and known value, and delivering the output from the multiplexer to an I/O driver.

Abstract: Exemplary embodiments of the present invention comprise a method for the support of a JTAG interface for the testing of connectivity between integrated circuits. The method comprises delivering output from a JTAG register to a primary register, delivering a JTAG control signal to the primary register and a clock signal gating control logic, delivering output from the primary register and a secondary register to a multiplexer, delivering clock signal output from the clock signal gating control logic to the multiplexer, wherein the clock signal is delivered is a constant and known value, and delivering the output from the multiplexer to an I/O driver.

Abstract: A system and method of detecting a fault in a transmission link are provided which includes providing a selectable reference level according to one of a direct current (DC) mode threshold and an alternating current (AC) mode threshold, wherein the DC mode threshold is a fixed potential and the AC mode threshold varies with time. An input signal arriving from the transmission link is compared to one of the DC mode threshold and the AC mode threshold to determine whether a fault is present in the transmission link.

Abstract: A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. A FIFO and serial logic circuitry is utilized to minimize the number of chip pins required to broadcast the information from the chip. The tracing technique utilizes instruction and data breakpoint debug functions to signal an external trace tool that a trace event has occurred.

Abstract: A method and apparatus for detecting the null byte at the end of a character string. The method and apparatus first logically concatenates two 32-bit input values into a single 64 bit value. Next, the 64-bit value is divided into 8 bytes. Then, a logical OR operation is performed on each byte and the results are put into an encoder. Finally, the encoder interprets the results of the OR operations and places output values into processor registers which indicate whether or where a null byte was detected.

Abstract: A computer memory subsystem is comprised of one or more Dynamic Random Access Memory (DRAM) arrays with on-chip sense latches for storing data outputted from the DRAM, an on-chip Static Random Access Memory (SRAM) functioning as a Distributed Cache and an on-chip multiplexor. A first data bus interconnects the sense latches, the SRAM and the multiplexor. A second data bus interconnects the multiplexor and the SRAM. A memory controller generates signals which cause information to be extracted from the DRAM while the contents of the SRAM is unchanged or vice versa.

Abstract: The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during performance of an interrupting task is prevented, thereby increasing the hit ratio of the cache when the interrupted task is resumed. Cache control information may be incorporated into a program status vector or program status word which is loaded into a program status register on occurrence of an interrupt.