Abstract: Epoxy probe cards are modified by mounting passive and/or active electronic components on the insulating surface of the probe card and connecting those components to the probe wires with short, electrically conductive lines that are formed on the probe card surface by printed circuit techniques. Ordinary wire probes may be interspersed with coaxial probes with electrically conducting tips bonded to electrically insulating shanks. An auxiliary printed circuit board containing additional electronic components may be included to accommodate especially sensitive test points. The resulting probe structure is intended to extend the frequency range of the well-developed epoxy probe card technology while retaining its ruggedness and low cost features.

Abstract: Epoxy probe cards are modified by mounting passive and/or active electronic components on the insulating surface of the probe card and connecting those components to the probe wires with short, electrically conductive lines that are formed on the probe card surface by printed circuit techniques. Ordinary wire probes may be interspersed with coaxial probes and probes with electrically conducting tips bonded to electrically insulating shanks. An auxiliary printed circuit board containing additional electronic components may be included to accommodate especially sensitive test points. The resulting probe structure is intended to extend the frequency range of the well-developed epoxy probe card technology while retaining its ruggedness and low cost features.

Abstract: Epoxy probe cards are modified by mounting passive and/or active electronic components on the insulating surface of the probe card and connecting those components to the probe wires with short, electrically conductive lines that are formed on the probe card surface by printed circuit techniques. Ordinary wire probes may be interspersed with coaxial probes and probes with electrically conducting tips bonded to electrically insulating shanks. An auxiliary printed circuit board containing additional electronic components may be included to accommodate especially sensitive test points. The resulting probe structure is intended to extend the frequency range of the well-developed epoxy probe card technology while retaining its ruggedness and low cost features.

Abstract: Epoxy probe cards are modified by mounting passive and/or active electronic components on the insulating surface of the probe card and connecting those components to the probe wires with short, electrically conductive lines that are formed on the probe card surface by printed circuit techniques. Ordinary wire probes may be interspersed with coaxial probes and probes with electrically conducting tips bonded to electrically insulating shanks. An auxiliary printed circuit board containing additional electronic components may be included to accommodate especially sensitive test points. The resulting probe structure is intended to extend the frequency range of the well-developed epoxy probe card technology while retaining its ruggedness and low cost features.

Abstract: A probe for testing integrated circuits at microwave frequencies employs a tapered coaxial transmission line to transform the impedance at the probe tips to the impedance of the test instruments. Mechanically resilient probe tip structures allow reliable probing of non-planar circuits and the elastic probe body allows large overprobing without damage to the test circuit. Novel insulator structures for the coaxial line allow easy and accurate assembly and high performance.

Abstract: A device for testing the performance of high speed integrated circuits (ICs) while in wafer form or separated from the wafer which includes first and second spaced-apart probes fixedly mounted on a support member for accurately positioning the first and second probes in three dimensions for contacting at least one first point and a second point, respectively, on an IC under test. The first and second probes are interconnected at a predetermined portion of their length by a capacitor means which provides sufficient flexibility so as to facilitate independent movement of the first and second probes and avoid introducing parameters (e.g., inductance) which interfere with high speed testing of the IC. In one embodiment, the first probe is a transmission line probe (e.g., a coaxial line) and the second probe is a wire probe for supplying power to the second point on the IC.

Abstract: A microposition table is held in place by the friction between a series of plates contacting one another. Movement is effected by forcing a small burst of air through a series of channels to drive metal pistons each held captive inside an elongated cylinder. The impact of each piston striking one or the other of the cylinder ends imparts sharp mechanical impulses to each plate driving the plate a small distance in the direction of the impacting force. Repeated impacts by repeated bursts of air move the plates the desired distances with respect to one another.

Abstract: A device for measuring the performance of high speed integrated circuits (ICs) while in wafer form consists of one or more miniature coaxial transmission lines for carrying the test signals to and from test instruments. Each of the miniature coaxial cables has a standard connector at one end for connection to testing instruments. The other end of each cable has its center conductor extended beyond the shield of the cable and formed into a conical point for connection to test pads on the IC. One or more miniature leaf springs are attached to the shield. The leaf springs are adapted so that during a probing operation they contact the test pads first and thereafter flex to allow the center conductors to make contact to other test pads. The miniature coaxial transmission lines also flex to limit forces which could otherwise damage center conductors or the test pads.

Abstract: An integrated circuit voltage reference (V.sub.REF) for MOS circuit utilization is supplied by the weighted difference amplification (30) of the voltages (V.sub.1, V.sub.1 ') developed by a pair of separate similar networks (10, 10' or 100, 100') each of which comprises a base-emitter junction of a bipolar semiconductor transistor (T.sub.1) whose emitter is connected to a first clocked voltage source (C.sub.1, C.sub.2, M.sub.1, M.sub.2) in a feedback loop of a difference amplifier (A.sub.1) and whose collector is connected to receive output of a second clocked voltage source (C.sub.3, C.sub.4, M.sub.3, M.sub.4) and to deliver output to a first input terminal of the difference amplifier (A.sub.1). In a preferred embodiment, a second input terminal of the difference amplifier (A.sub.1) is supplied by the output voltage of an auxiliary voltage source (C.sub.5, C.sub.6, M.sub.6, M.sub.7, M.sub.8, M.sub.9) which is in another feedback loop of this amplifier (A.sub.1).

Abstract: This invention involves a capacitor memory cell (C.sub.S) of, typically the metal-oxide-semiconductor (MOS) capacitor type, which is accessed for reading and writing by means of an access network connected to the memory cell through a gating transistor (T.sub.1), and which is provided with an independent refresh network for maintaining the memory state of the cell in the absence of an access writing signal. The refresh network includes a pair of MOSFET (Metal Oxide Semiconductor Field-Effect Transistors) transistors (T.sub.2, T.sub.3) connected between the MOS capacitor and an A.C. refresh line which is independent of the electrical access network. Either a "full" or "empty" capacitor memory state, binary digital 1 or 0, respectively, is maintained without the need for interrupting the reading and writing of the MOS capacitor.

Abstract: A voltage multiplier circuit, in MOS technology, is arranged whereby MOS capacitors are alternately connected together in parallel (charging phase) and series (multiplying phase). Each capacitor is provided with a separate input MOS transistor as well as a separate feedback loop from the output side of each capacitor to the gate electrode of its input MOS transistor. During the multiplying phase, each input transistor is turned "on" in response to the voltage supplied by each feedback loop, thereby connecting the capacitors in series.

Abstract: An IGFET push-pull driver circuit includes an output stage having pull-up and pull-down IGFETs for driving an output node. An inverter stage drives the gate of the pull-up IGFET. A current sensing IGFET biased to represent a resistance is coupled between the pull-up IGFET and the output node to provide a voltage drop which is proportional to the current flowing through the pull-up IGFET. A regulating IGFET with its channel coupled between the gate of the pull-up IGFET and the output node and with its gate coupled to the juncture of the pull-up IGFET and the current sensing IGFET, responds to the voltage drop across the current sensing IGFET to provide feedback control of the conductance of the pull-up IGFET. The maximum output current of the driver is limited to a value which remains substantially constant over a wide range of processing parameters, operating temperature and load impedance.

Abstract: This invention involves a detector circuit in MOS technology for sensing "loss of clock"; that is, whenever a clock input voltage pulse source is interrupted or stops (becomes "stuck") at any level, the output voltage of the detector circuit is at a high level, but is at a low level when the clock is working properly. Such a circuit is achieved by means of a first MOS electrical inverter (I.sub.1), connected for feeding its output to an MOS electrical differentiator (.DELTA.), connector for feeding its output to a thresholding MOS amplifier (A), connected for feeding its output to a unidirectional MOS current inhibitor (D), connected for feeding its output to a second MOS electrical inverter (I.sub.2), connected in parallel with a storage capacitor (C) in parallel with a leakage current source (J.sub.L), whereby the output of the second inverter is a binary indication of the presence vs. absence of clock pulse input to the first inverter.