Abstract: Digital loop carrier system having CPU to channel unit protocol. A method of communicating with the protocol is used in a telecommunication system having at least a central processing unit (CPU) connected to a plurality of digital interface units (DIU) via a communication module (CM). Each of the digital interface units is connected to a plurality of channel units (CU).

Abstract: The test access system of the present invention is for use in a digital loop carrier communication system having at least first and second terminals connected by a digital transmission line. Each of the first and second terminals has a plurality of analog ports for analog signals and at least one digital port connected to the digital transmission line for digital signals. Each of the first and second terminals also has a plurality of channel units having first ports connected to the analog ports, respectively, and at least one digital interface unit having a first port connected to the channel units and a second port connected to the digital port. The test access system has a channel diagnostic unit connected via a first bus to each of the analog ports and the first ports of the channel units and connected via a second bus to the first port of the digital interface unit.

Abstract: A system for allocating a plurality of channel units to a transmission line having a plurality of timeslots including bandwidth and multiple time slot allocation. The system has a counter and a parallel to serial register for providing a channel address via an address signal corresponding to a predetermined one of the plurality of timeslots to each of the channel units. A processor is provided for assigning an assigned address to each channel unit of the plurality of channel units, such channel unit being assigned to a different selected timeslot of the plurality of timeslots. Each of the channel units has a comparator for comparing the channel address in the address signal to the assigned address, the channel unit upon having a correspondence between the channel address and the assigned address, transmitting and receiving on the transmission line. A bus connects the plurality of channel units to the means for addressing.

Abstract: A system having a plurality of channel units for connection to a transmission line having a plurality of timeslots. The system has a counter and a parallel to serial register for providing a channel address via an address signal corresponding to a predetermined one of the plurality of timeslots to each of the channel units. A processor is provided for assigning an assigned address to each channel unit of the plurality of channel units, such channel unit being assigned to a different selected timeslot of the plurality of timeslots. Each of the channel units has a comparator for comparing the channel address in the address signal to the assigned address, the channel unit upon having a correspondence between the channel address and the assigned address, transmitting and receiving on the transmission line. A bus connects the plurality of channel units to the means for addressing. An active channel unit has the ability to request communication with the processor by an interrupt signal.

Abstract: There is disclosed an automatic line buildout circuit which includes in its signal path two variable filters, each implemented by a transconductance operational amplifier circuit. Each filter exhibits a transfer function pole with a frequency which is directly related to a control current applied to that filter. At a point in the signal path after the two variable filters, there is a peak detector which provides an output level proportional to the peak amplitude of the signal in the path, and therefore proportional to the cable length. From the peak detector output level, there is derived for each of the variable filters a control current, related to the output level by a preselected function. For each variable filter, the associated function expresses the relation between cable length and the filter cutoff frequency which is required for proper equalization.

Abstract: A framing circuit for a pulse code modulated, time multiplexed data receiver provides terminal framing by first detecting a predetermined terminal frame bit code and then checking for false framing by utilizing a false framing detector to count the number of times a particular pattern in a signaling frame bit code occurs. The false framing detector is enabled after terminal framing of the receiver has been accomplished. The false framing detector thereby provides a cross-check between the terminal frame code and the signaling frame code to assure that the receiver has not erroneously framed on a 2 khz interference tone. The cross-check occurs during data reception after terminal framing so that the false frame detector does not delay reframing under ordinary circumstances.