Patents by Inventor Harry J. Geyer

Harry J. Geyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6805778
    Abstract: Methods used in semiconductor electroplating systems, such as for plating copper, onto a semiconductor wafer or other semiconductor workpiece. The methods apply to patterned metal layers plated onto a seed layer which is partially protected by an overlying photoresist or other coating. The methods employ an electrode assembly which has a boot which seals about a contact face of the electrode. The sealing is performed by engaging the seal against photoresist to prevent corrosion of the seal layer. The area enclosed by the sealing includes a via which is surrounded by the seal. The electrode contact extends through the via to provide electrical contact with the metallic seed layer. Plating of copper or other metal proceeds at exposed seed layer areas.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: October 19, 2004
    Assignee: Semitool, Inc.
    Inventors: Robert W. Batz, Jr., Kenneth C. Haugan, Harry J. Geyer, Robert W. Berner
  • Publication number: 20040035707
    Abstract: Methods used in semiconductor electroplating systems, such as for plating copper, onto a semiconductor wafer or other semiconductor workpiece. The methods apply to patterned metal layers plated onto a seed layer which is partially protected by an overlying photoresist or other coating. The methods employ an electrode assembly which has a boot which seals about a contact face of the electrode. The sealing is performed by engaging the seal against photoresist to prevent corrosion of the seal layer. The area enclosed by the sealing includes a via which is surrounded by the seal. The electrode contact extends through the via to provide electrical contact with the metallic seed layer. Plating of copper or other metal proceeds at exposed seed layer areas.
    Type: Application
    Filed: April 7, 2003
    Publication date: February 26, 2004
    Inventors: Robert W. Batz, Kenneth C. Haugan, Harry J. Geyer, Robert W. Berner
  • Patent number: 6461494
    Abstract: Methods used in semiconductor electroplating systems, such as for plating copper, onto a semiconductor wafer or other semiconductor workpiece. The methods apply to patterned metal layers plated onto seed layer which is partially protected by an overlying photoresist or other coating. The methods employ an electrode assembly which has a boot which seals about a contact face of the electrode. The sealing is performed by engaging the seal against photoresist to prevent corrosion of the seal layer. The area enclosed by the sealing includes a via which is surrounded by the seal. The electrode contact extends through the via to provide electrical contact with the metallic seed layer. Plating of copper or other metal proceeds at exposed seed layer areas.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: October 8, 2002
    Assignee: Semitool, Inc.
    Inventors: Robert W. Batz, Jr., Kenneth C. Haugan, Harry J. Geyer, Robert W. Berner
  • Patent number: 6001234
    Abstract: Methods used in semiconductor electroplating systems, such as for plating copper, onto a semiconductor wafer or other semiconductor workpiece. The methods apply to patterned metal layers plated onto a seed layer which is partially protected by an overlying photoresist or other coating. The methods employ an electrode assembly which has a boot which seals about a contact face of the electrode. The sealing is performed by engaging the seal against photoresist to prevent corrosion of the seal layer. The area enclosed by the sealing includes a via which is surrounded by the seal. The electrode contact extends through the via to provide electrical contact with the metallic seed layer. Plating of copper or other metal proceeds at exposed seed layer areas.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: December 14, 1999
    Assignee: Semitool, Inc.
    Inventors: Robert W. Batz, Jr., Kenneth C. Haugan, Harry J. Geyer, Robert W. Berner
  • Patent number: 5467253
    Abstract: A semiconductor device having a substrate support (22) and a method of forming the semiconductor device. A substrate (11) has conductive traces (12) and a bonding pad (13) on a bottom surface and conductive traces (14) and a semiconductor chip attach pad (17) on a top surface. The substrate support (22) has an aperture (23) and is coupled to the substrate (11). A semiconductor chip (31) is coupled to the semiconductor chip attach pad (17). The semiconductor chip (31) is covered by an encapsulating material (38) or a cap (41, 51) which provide protection for the semiconductor chip (31).
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: November 14, 1995
    Assignee: Motorola, Inc.
    Inventors: James K. Heckman, Francis J. Carney, Harry J. Geyer
  • Patent number: 5240165
    Abstract: A method of producing reliable bonds of a lead to a bump on a semiconductor chip is accomplished by controlling the amount of deformation of the lead and the bump during bonding. A differential amplifier is used to sense the deformation and stop the application of force to the lead and the bump when a desired amount of deformation of the lead and the bump is obtained.
    Type: Grant
    Filed: July 6, 1992
    Date of Patent: August 31, 1993
    Assignee: Motorola, Inc.
    Inventors: Harry J. Geyer, Ronald M. Lahti
  • Patent number: 5232144
    Abstract: An improved TAB bond is achieved by an apparatus for tape automated bonding, comprising a thermode having a bonding surface. A shield is attached around the bonding surface. The shield is designed so that a nonoxidizing gas may be distributed in a bonding space defined by a plurality of tape leads on a tape positioned below the shield and a bonding area of a semiconductor chip positioned below the tape and the plurality of tape leads. In the bonding position the flow of the nonoxidizing gas removes substantially all of an ambient air in the bonding space.
    Type: Grant
    Filed: June 26, 1992
    Date of Patent: August 3, 1993
    Assignee: Motorola, Inc.
    Inventors: Francis J. Carney, Harry J. Geyer, Renee M. Gregg
  • Patent number: 4943708
    Abstract: A module is described for use in data devices such as smart cards. The module consists of a contact carrier having contacts, an integrated circuit, and a base enclosing the integrated circuit. The base is formed to provide a groove around the perimeter such that when the device is formed, material from an intermediate layer will flow into the groove and secure the module to the card.
    Type: Grant
    Filed: February 1, 1988
    Date of Patent: July 24, 1990
    Assignee: Motorola, Inc.
    Inventors: Marion I. Simmons, Harry J. Geyer
  • Patent number: 4927505
    Abstract: A titanium-tungsten-nitride/titanium-tungsten/gold (TiWN/TiW/Au) packaging interconnect metallization scheme is used to provide electrical contact to chip level interconnect metallization on a semiconductor substrate. The TiWN/TiW/Au packaging interconnect metallization scheme provides for good adhesion and barrier properties that withstand high temperatures and improve the reliability of the semiconductor chip. The TiWN layer provides good adhesion to the chip level interconnect metallization and the passivation layer. It also provides improved barrier properties to prevent the diffusion of other metal atoms through it. The TiW layer provides good adhesion to the gold metal layer. A gold bump may be electroplated to the gold layer and automatically bonded to a conductive lead of a tape in TAB packaging; or a wire bonded to the gold layer in conventional packaging.
    Type: Grant
    Filed: July 28, 1989
    Date of Patent: May 22, 1990
    Assignee: Motorola Inc.
    Inventors: Ravinder K. Sharma, Harry J. Geyer, Douglas G. Mitchell
  • Patent number: 4880708
    Abstract: A titanium-tungsten-nitride/titanium-tungsten/gold (TiWN/TiW/Au) packaging interconnect metallization scheme is used to provide electrical contact to chip level interconnect metallization on a semiconductor substrate. The TiWN/TiW/Au packaging interconnect metallization scheme provides for good adhesion and barrier properties that withstand high temperatures and improve the reliability of the semiconductor chip. The TiWN layer provides good adhesion to the chip level interconnect metallization and the passivation layer. It also provides improved barrier properties to prevent the diffusion of other metal atoms through it. The TiW layer provides good adhesion to the gold metal layer. A gold bump may be electroplated to the gold layer and automatically bonded to a conductive lead of a tape in TAB packaging; or a wire bonded to the gold layer in conventional packaging.
    Type: Grant
    Filed: July 5, 1988
    Date of Patent: November 14, 1989
    Assignee: Motorola, Inc.
    Inventors: Ravinder K. Sharma, Harry J. Geyer, Douglas G. Mitchell
  • Patent number: 4795077
    Abstract: A method for bonding which comprises the step of heating a bottom thermode to a temperature of approximately 150.degree. C. The bottom thermode is then pulse heated to approximately 350.degree. C. while a die and lead frame are disposed above the lower thermode. An upper thermode, which may remain unheated, is then lowered to cause contact between the lead frame and the contacts of the die. The lower thermode then returns to a temperature of approximately 150.degree. C. The pulse heating of the lower thermode lasts for approximately 1-3 seconds.
    Type: Grant
    Filed: May 23, 1988
    Date of Patent: January 3, 1989
    Assignee: Motorola Inc.
    Inventors: Harry J. Geyer, James H. Knapp, Setsuko J. Cole
  • Patent number: 4003073
    Abstract: Wire bonding is eliminated in the assembly of microelectronic devices, by a process involving the direct bonding of circuit electrodes to an unsupported metallic sheet-frame member having a plurality of inwardly extending leads. A single-step vibratory pressure welding technique is employed for the simultaneous bonding of all leads to a semiconductor integrated circuit chip. Lateral confinement of the leads during the bonding steps causes a buckling action to introduce a small but critical loop in each lead to ensure clearance between the lead fingers and the perimeter of the semiconductor chip, whereby electrical shorting is avoided. The loop also provides a structural flexibility in the leads, which tends to protect the bonding sites from excessive stresses. Subsequently, the first frame member including the bonded circuit is attached, preferably by resistance welding, to a second lead frame member of heavier gage and increased dimensions, suitable for connection with external circuitry.
    Type: Grant
    Filed: October 10, 1972
    Date of Patent: January 11, 1977
    Assignee: Motorola, Inc.
    Inventors: Robert W. Helda, Harry J. Geyer