Abstract: A method for programming a non-memory device comprising a plurality of resistive switching device. Each of the plurality of resistive switching device includes a resistive switching material characterized by a resistance characterized by a state depending on a conductive filament structure. A first programming code file to configure a system to perform a predetermined task is provided. The programmability of each of the plurality of resistive switching device is maintained. The system receives the first programming code file, executing the first programming code file, and verifies and validates that the system performs the predetermined task. Once the first programming code file is validated, the conductive filament in one or more resistive switching device is fixed spatially in a portion of the resistive switching material of the respective one or more resistive switching device by applying joule heating programming. The programmability of each of the memory device is removed.

Abstract: A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.

Abstract: An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Abstract: Providing for capacitive programming of two-terminal memory devices is described herein. By way of example, a capacitance circuit can be precharged to a predetermined program voltage to facilitate programming one or more memory cells. The capacitance circuit can be disconnected from a power source and connected instead to the memory cell(s), enabling charge stored by the capacitance circuit to discharge through the memory cell(s). A current at the memory cell(s) can program the cell, while a total amount of discharge is limited to the charge stored by the capacitance circuit. Limiting the total charge can serve to also limit joule heating of the target memory cell, power consumption of a memory device, as well as other benefits.

Abstract: Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Abstract: A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.

Abstract: A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.

Abstract: A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.

Abstract: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Abstract: A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit. A plurality of bit lines is provided, each bit line being coupled to the first end of one of the resistive memory cells. A plurality of select transistors is provided, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit. First and second global word lines are provided, each global word line being coupled to a control terminal of at least one select transistor. First and second source lines are provided, each source line being coupled to a source terminal of at least one select transistor.

Abstract: A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.

Abstract: Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.

Abstract: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Abstract: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Abstract: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Abstract: An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.

Abstract: A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.

Abstract: An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.

Abstract: Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.