Abstract: A method of treating one or more damaged hair shafts, each hair shaft including a cuticle layer and a cortex enclosed in the cuticle layer is disclosed. The method comprises: selecting one or more polymers that can penetrate the hair shafts with a pore size of about 5 angstroms to about 5000 angstroms; and treating the hair shafts by applying an effective amount of a composition containing said anionic polymers to said hair shafts.

Abstract: A method of treating one or more hair shafts, each hair shaft including a cuticle layer and a cortex enclosed in the cuticle layer is disclosed. The method comprises: selecting one or more polymers that can penetrate the hair shafts with a pore size of about 5 angstroms to about 5000 angstroms; and treating the hair shafts by applying an effective amount of a composition containing said polymers to said hair shafts.

Abstract: Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, such as, for example, including a state machine, to generate deterministic data to be written to the pseudo random memory addresses. Computer systems and other electronic systems including such apparatus are also disclosed.

Abstract: In one embodiment, an electronic device comprises a plurality of electrical switches and a plurality of energy storage elements arrayed relative to one another such that the energy storage elements may be connected in series, or in parallel, or both, to an input and an output.

Abstract: A design evaluation system 10 which evaluates a design 44 of a component or assembly, such as component or assembly 12. Particularly, system 10 includes a database 30 having several equality and inequality relationships which are required to be satisfied by the design 44. System 10 also includes several equality and inequality relationships which system 10 attempts to have satisfied by the design 44, but which are not required to be satisfied. System 10 further dynamically modifies the values of certain variables within the design 44 in order to substantially ensure that the design 44 is modified in a manner which is consistent with certain of the equality and inequality relationships which are contained within the database 30.

Abstract: A novel apparatus and methods provide the capability to structural test device input/output pins which are not connected to an external tester during the testing process. The method does not require a new Design For Test logic block, but rather, the method modifies existing registers on the chip to function as a (Pseudo Random Pattern Generator) PRPG and a MISR (Multiple Input Signature Register). The PRPG generates input patterns. The MISR generates an output signature. PRPG and MISR are both based on LFSR (Linear Feedback Shift Register). This allows running a random pattern generated by the PRPG, testing at-speed a path from the PRPG through the I/O logic circuitry interfacing to core logic, and storing a signature pattern in the MISR. The testing will take place at native speed of the device and no connection to the pins is required externally.

Abstract: A system for providing IP centric, multi-channel, telecommunication services such as television on demand, video on demand, karaoke on demand, Internet access, and telephone services, said system comprising: (1) a media content creator subsystem for converting multiple format incoming video signal streams corresponding to multiple program files into IP based packets ready for transmission over a broadband network, the media content creator converting the incoming video signals into digital data and compressing the digital data based on multiple encoding standards into IP based packets; (2) a media streaming subsystem for storing the IP based packets, wherein the media streaming engine is capable of providing multiple streams of IP based packets for transmission based on user request, and wherein each stream of IP based packets represents the converted and encoded content of one user requested program; and (3) a content management subsystem for user authentication, billing, digital rights management protection

Abstract: The invention involves a system and a method of inspecting a selected part design from an inventory of computer-aided part designs for die compliance as to the part design's geometric characteristics of die lock, draft, and sharp edge. The invention provides for an improvement of inspecting a computer-aided part design in order to lessen insufficient inspections which lead to manufacturing infeasibilities. The invention includes selecting a part design, defining a die open direction, evaluating die lock and draft characteristics of the selected part design, and evaluating sharp edge characteristics of the selected part design.

Abstract: A novel apparatus and methods are described. The apparatus and method provide the capability to structural test device input/output pins which are not connected to an external tester during the testing process. The method does not require a new Design For Test logic block, but rather, the method modifies existing registers on the chip to function as a (Pseudo Random Pattern Generator) PRPG and a MISR (Multiple Input Signature Register). The PRPG generates input patterns. The MISR generates an output signature. PRPG and MISR are both based on LFSR (Linear Feedback Shift Register). This allows running a random pattern generated by the PRPG, testing at-speed a path from the PRPG through the I/O logic circuitry interfacing to core logic, and storing a signature pattern in the MISR. Since the testing will take place at native speed of the device and no connection to the pins is required externally, it fulfills a key gap in the manufacturing test environment on low cost and low pin count testers.

Abstract: The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop (“PLL”) circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period.

Abstract: A storage subsystem for use in a data processing system having real and extended storage, a vector processor and a store-in cache buffer. Transfers between real and extended storage are performed with a store buffer external to the cache, but comparable in size to the line size of the cache directly associated with the real storage. Hard data errors in the cache are corrected with hardware invert-retry mechanism which operates in response to a machine check and does the correction as a part of the instruction retry. Vector processor storage operations bypass the cache and transfer data directly from storage to the vector processor.

Abstract: A method and an apparatus utilizing mux scan flip-flops to test for timing-related defects. In one embodiment, a delay circuit is used to act as a buffer for a scan enable signal received by the mux scan flip-flops of a test circuit. The scan mode signal is first sent to the delay circuit, which then distributes the scan mode signal to the mux scan flip-flops. Since each delay circuit can serve as the buffer for numerous mux scan flip-flops, the scan mode signal may be sent initially to a smaller number of delay circuits instead of the thousands of mux scan flip-flops that may be distributed throughout the entire integrated circuit. Furthermore, in one embodiment the delay circuit delays propagation of active-to-inactive transitions of the scan enable signal by one clock cycle, synchronizing the system clock cycle with the active-to-inactive transitions of the scan mode signal. In one embodiment, inactive-to-active transitions of the scan enable signal are propagated without the one clock cycle delay.

Abstract: A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

Abstract: During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.