Abstract: A computer design system is used to map a logical hierarchy corresponding to the logical functions of an electronic system into a physical hierarchy corresponding to the physical positioning of the actual electronic components which will implement the logical functions of the system. The logical hierarchy contains several levels of logical entities connected by signals, and the physical hierarchy contains physical packages corresponding to electronic components, such as integrated circuits. The mapping is accomplished by designating partition group assertions (PGAs) for each of the logical entities in the logical hierarchy. Each PGA corresponds to one of the physical packages in the physical hierarchy. Each entity is grouped by common PGA designation, and each signal of each entity is classified as external, if the signal connects entities located on different physical packages, or internal, if the signal connects entities located on the same physical package.