Abstract: A single clock mesh is configured to provide a first clock signal at a first frequency. A number of divided clock signals are generated, each divided clock signal being at a frequency that is a respective integer division of the first frequency. The divided clock signals are received from a divider and output by a clock controller along with corresponding enable signals. For each divided clock, a shaped clock signal is generated. The shaped clock signal has rising edges and falling edges that algin with rising edges and falling edges of the first clock signal provided by the single clock mesh.

Abstract: A system and method of detecting a fault in a transmission link are provided which includes providing a selectable reference level according to one of a direct current (DC) mode threshold and an alternating current (AC) mode threshold, wherein the DC mode threshold is a fixed potential and the AC mode threshold varies with time. An input signal arriving from the transmission link is compared to one of the DC mode threshold and the AC mode threshold to determine whether a fault is present in the transmission link.