Patents by Inventor Harry Michael Siegel
Harry Michael Siegel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8163645Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.Type: GrantFiled: July 30, 2010Date of Patent: April 24, 2012Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
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Publication number: 20100297841Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.Type: ApplicationFiled: July 30, 2010Publication date: November 25, 2010Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
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Patent number: 7786582Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.Type: GrantFiled: June 19, 2006Date of Patent: August 31, 2010Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
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Patent number: 7595017Abstract: A system and method is disclosed for using a pre-formed film in a transfer molding process of the type that uses a transfer mold to encapsulate portions of an integrated circuit with a molding compound. A film of compliant material is pre-formed to conform the shape of the film to a mold cavity surface of the transfer mold. The pre-formed film is then placed adjacent to the surfaces of the mold cavity of the transfer mold. The mold cavity is filled with molding compound and the integrated circuit is encapsulated. The pre-formation of the film allows materials to be used that are not suitable for use with prior art methods.Type: GrantFiled: January 31, 2002Date of Patent: September 29, 2009Assignee: STMicroelectronics, Inc.Inventors: Harry Michael Siegel, Anthony M. Chiu
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Patent number: 7456050Abstract: A system and method is disclosed for controlling a height and a planarity of an integrated circuit die. In one advantageous embodiment of the invention, a plurality of patterned metal stops are fabricated on an integrated circuit substrate and covered with die attach material. An integrated circuit die is inserted into the die attach material and placed into a clamping mechanism of a molding machine. The clamping mechanism (1) compresses the die into the die attach material, (2) rotates the die into parallel alignment with the substrate, and (3) pushes the die into contact with the patterned metal stops. In this manner the die height and the die planarity are precisely controlled.Type: GrantFiled: July 1, 2003Date of Patent: November 25, 2008Assignee: STMicroelectronics, Inc.Inventors: Harry Michael Siegel, Robert Henry Bond, Tom Quoc Lao
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Patent number: 7202110Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.Type: GrantFiled: December 6, 2004Date of Patent: April 10, 2007Assignee: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Harry Michael Siegel
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Patent number: 7109574Abstract: An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; 2) an integrated circuit (IC) package for supporting the IC die, wherein the IC package is attached to at least one of the sidewalls of the IC die such that at least a portion of the IC die first surface and at least a portion of the IC die second surface are exposed; and 3) at least one auxiliary component attached to at least one of the exposed portion of the IC die first surface and the exposed portion of the IC die second surface.Type: GrantFiled: March 27, 2003Date of Patent: September 19, 2006Assignee: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Harry Michael Siegel
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Patent number: 7096581Abstract: An integrated circuit includes a portion having at least one active circuit area. The integrated circuit also includes a redistribution metal layer fabricated at least partially during fabrication of the portion of the integrated circuit. A method for fabricating an integrated circuit includes fabricating a portion of the integrated circuit, where the portion includes at least one active circuit area. The method also includes fabricating a redistribution metal layer at least partially during fabrication of the portion of the integrated circuit.Type: GrantFiled: March 6, 2002Date of Patent: August 29, 2006Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
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Patent number: 7098065Abstract: An integrated lid for microelectromechanical system (MEMS) devices is formed from a nitride layer deposited over a cavity containing movable parts for the device. Pillars are formed through openings within large area movable parts to support the lid over those parts. Slides are formed and moved under large etchant openings through the lid to allow the openings to be sealed by sputtering.Type: GrantFiled: September 28, 2004Date of Patent: August 29, 2006Assignee: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Harry Michael Siegel
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Patent number: 6951125Abstract: A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits a form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.Type: GrantFiled: January 31, 2002Date of Patent: October 4, 2005Assignee: STMicroelectronics, Inc.Inventors: Harry Michael Siegel, Anthony M. Chiu
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Patent number: 6900508Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.Type: GrantFiled: April 16, 2002Date of Patent: May 31, 2005Assignee: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Harry Michael Siegel
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Patent number: 6785137Abstract: A method for removing heat from an active area of an integrated circuit device is provided. The method includes applying a separator to the active area of the integrated circuit device. A thermally conductive element is coupled to the active area of the integrated circuit device outwardly of the separator.Type: GrantFiled: July 26, 2002Date of Patent: August 31, 2004Assignee: STMicroelectronics, Inc.Inventor: Harry Michael Siegel
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Patent number: 6771500Abstract: The invention comprises a lid that is capable of being placed in contact with and attached to an integrated circuit that has an exposed surface of an integrated circuit die. The lid has portions that form a cavity between a surface of the lid and the exposed surface of the integrated circuit die when the lid is placed in contact with the integrated circuit. The lid also has portions that form a first fluid conduit for transporting a fluid into the cavity and a second fluid conduit for transporting the fluid out of the cavity. Heat from the integrated circuit die is absorbed by the fluid by direct convection and removed from the integrated circuit when the fluid is removed from the cavity.Type: GrantFiled: March 27, 2003Date of Patent: August 3, 2004Assignee: STMicroelectronics, Inc.Inventors: Harry Michael Siegel, Anthony M. Chiu
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Publication number: 20040017661Abstract: A method for removing heat from an active area of an integrated circuit device is provided. The method includes applying a separator to the active area of the integrated circuit device. A thermally conductive element is coupled to the active area of the integrated circuit device outwardly of the separator.Type: ApplicationFiled: July 26, 2002Publication date: January 29, 2004Applicant: STMicroelectronics, Inc.Inventor: Harry Michael Siegel
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Publication number: 20040017000Abstract: An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; 2) an integrated circuit (IC) package for supporting the IC die, wherein the IC package is attached to at least one of the sidewalls of the IC die such that at least a portion of the IC die first surface and at least a portion of the IC die second surface are exposed; and 3) at least one auxiliary component attached to at least one of the exposed portion of the IC die first surface and the exposed portion of the IC die second surface.Type: ApplicationFiled: March 27, 2003Publication date: January 29, 2004Applicant: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Harry Michael Siegel
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Publication number: 20030193072Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.Type: ApplicationFiled: April 16, 2002Publication date: October 16, 2003Applicant: STMICROELECTRONICS, INC.Inventors: Anthony M. Chiu, Harry Michael Siegel
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Publication number: 20030167632Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.Type: ApplicationFiled: March 6, 2002Publication date: September 11, 2003Applicant: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
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Patent number: 6603192Abstract: Passivation for capacitive sensor circuits, which overlies the capacitive sensor electrodes and is normally conformal to the electrodes and the underlying interlevel dielectric, is planarized by forming a layer of flowable oxide over the electrodes before forming the passivation. The flowable oxide, which is preferably very thin over the electrodes to minimize loss of sensitivity, provides a substantially planar upper surface, so that passivation formed on the flowable oxide is also substantially planar. Alternatively, a deposited oxide planarized by chemical mechanical polishing may be employed to planarize the surface on which a passivation stack is formed. The planarized passivation provides markedly improved scratch resistance.Type: GrantFiled: July 30, 1999Date of Patent: August 5, 2003Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Harry Michael Siegel
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Publication number: 20030143406Abstract: A system and method is disclosed for using a pre-formed film in a transfer molding process of the type that uses a transfer mold to encapsulate portions of an integrated circuit with a molding compound. A film of compliant material is pre-formed to conform the shape of the film to a mold cavity surface of the transfer mold. The pre-formed film is then placed adjacent to the surfaces of the mold cavity of the transfer mold. The mold cavity is filled with molding compound and the integrated circuit is encapsulated. The pre-formation of the film allows materials to be used that are not suitable for use with prior art methods.Type: ApplicationFiled: January 31, 2002Publication date: July 31, 2003Applicant: STMicroelectronics, Inc.Inventors: Harry Michael Siegel, Anthony M. Chiu
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Publication number: 20030140678Abstract: A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits to form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.Type: ApplicationFiled: January 31, 2002Publication date: July 31, 2003Applicant: STMicroelectronics, Inc.Inventors: Harry Michael Siegel, Anthony M. Chiu