Abstract: An improved circuit for generating a crosstalk noise cancellation signal may be used for combining the crosstalk noise cancellation signal with a victim signal without a crosstalk cancelling capacitor. The improved crosstalk cancellation circuit may be used to provide improved TX crosstalk cancellation, and may be used to provide improved performance of increasingly higher speed memory systems regardless of memory process technology, enabling improvements to existing and future memory systems and other communication systems. The improved crosstalk cancellation circuit may include a transmission amplifier to receive a first digital signal and generate a first analog output signal, a crosstalk cancellation circuit to receive the second digital signal and generate an analog cancellation signal, and a first conductive node to generate a first crosstalk canceled signal by combining the first analog output signal with the analog cancellation signal.

Abstract: Embodiments herein relate to an interconnect that includes a first repeater, a second repeater, and a wire configured to carry an electrical signal from the first repeater to the second repeater. The wire may have a measurement adjacent to the first repeater that is greater than a measurement of the wire adjacent to the second repeater. Other embodiments may be described and claimed.

Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) TO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

Abstract: Some embodiments include apparatuses having an electrostatic discharge (ESD) protection circuit coupled to a node, and first, second, and third circuits coupled to the node. The first circuit includes a first charge pump to cause a voltage at the node during activation of the first circuit to change from a first voltage value to a second voltage value within first multiple periods of a clock signal, the second voltage value being less than the first voltage value. The second includes a second charge pump to cause a voltage at the node during activation of the second circuit to change from a third voltage value to a fourth voltage value during second multiple periods of the clock signal, the fourth voltage value being greater than the third voltage value. The third circuit generates information based on the values of the voltage at the node during activation of the first and second circuits. The apparatuses optionally include a fourth circuit to generate an additional voltage at an additional node.

Abstract: Some embodiments include an apparatus including a first node to receive an input data signal including a first edge, and a second edge occurring after the first edge; a second node to receive a strobe signal including an edge; a first circuit to generate a modified strobe signal based on the strobe signal, the modified strobe signal including an edge occurring after the edge of the strobe signal; a second circuit to generate a modified data signal based on the input data signal, the modified data signal including an edge occurring after the second edge of the input data signal; and a third circuit to respond to the modified strobe signal and generate an output data signal based on the modified data signal.

Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.

Abstract: Some embodiments include an apparatus including a first node to receive an input data signal including a first edge, and a second edge occurring after the first edge; a second node to receive a strobe signal including an edge; a first circuit to generate a modified strobe signal based on the strobe signal, the modified strobe signal including an edge occurring after the edge of the strobe signal; a second circuit to generate a modified data signal based on the input data signal, the modified data signal including an edge occurring after the second edge of the input data signal; and a third circuit to respond to the modified strobe signal and generate an output data signal based on the modified data signal.

Abstract: An apparatus is described that includes a memory channel driver circuit having first driver circuitry to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.

Abstract: Some embodiments include apparatus and methods using circuits to receive an input signal, generate an equalized signal, provide the equalized signal to a node, amplify the equalized signal, and generate digital input information from the equalized signal. A delay circuit, including delay elements, is provided to apply a time delay to the digital input information and generate digital output information. A selector in the delay circuit provides feedback information from an output node of one of the delay elements. An adjust circuit, including switches on circuit paths coupled to the node, is provided to control the switches based on the feedback information.

Abstract: Some embodiments include apparatuses having an electrostatic discharge (ESD) protection circuit coupled to a node, and first, second, and third circuits coupled to the node. The first circuit includes a first charge pump to cause a voltage at the node during activation of the first circuit to change from a first voltage value to a second voltage value within first multiple periods of a clock signal, the second voltage value being less than the first voltage value. The second includes a second charge pump to cause a voltage at the node during activation of the second circuit to change from a third voltage value to a fourth voltage value during second multiple periods of the clock signal, the fourth voltage value being greater than the third voltage value. The third circuit generates information based on the values of the voltage at the node during activation of the first and second circuits. The apparatuses optionally include a fourth circuit to generate an additional voltage at an additional node.

Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.

Abstract: A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.

Abstract: An apparatus is described that includes a memory channel driver circuit having first driver circuity to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.

Abstract: Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system. Specifically, the system may include a processor chip which may include an on-die voltage regulator (VR) configured to supply a voltage to a component of the processor chip. The processor chip may be coupled with a dynamic random access memory (DRAM). The system may further include an external VR coupled with the DRAM. A BIOS may be configured to regulate the voltage output of one or both of the on-die VR and/or the external VR. Other embodiments may be described or claimed.

Abstract: Some embodiments include apparatus and methods using circuits to receive an input signal, generate an equalized signal, provide the equalized signal to a node, amplify the equalized signal, and generate digital input information from the equalized signal. A delay circuit, including delay elements, is provided to apply a time delay to the digital input information and generate digital output information. A selector in the delay circuit provides feedback information from an output node of one of the delay elements. An adjust circuit, including switches on circuit paths coupled to the node, is provided to control the switches based on the feedback information.

Abstract: Described is an apparatus which comprises: a first buffer to receive a first signal from a first transmission media; a second buffer to receive a second signal from a second transmission media separate from the first transmission media; a first summing node coupled to the first buffer, the first summing node to receive output of the first buffer; and a first digital adjustment circuit which is operable to drive a first adjustment signal to the first summing node when a transition edge of the second signal is detected.

Abstract: Embodiments include apparatuses, methods, and systems for crosstalk compensation. In embodiments, a transmitter may include a crosstalk compensation circuit that may receive a victim data signal and one or more attacker data signals. The crosstalk compensation circuit may adjust the timing of transitions in the victim data signal based on detected transitions in the one or more attacker data signals. Other embodiments may be described and claimed.

Abstract: Embodiments include apparatuses, methods, and systems for crosstalk compensation. In embodiments, a transmitter may include a crosstalk compensation circuit that may receive a victim data signal and one or more attacker data signals. The crosstalk compensation circuit may adjust the timing of transitions in the victim data signal based on detected transitions in the one or more attacker data signals. Other embodiments may be described and claimed.