Abstract: A method of performing a fast information compare within a processor which includes performing a more significant bit compare when information is loaded into a translation lookaside buffer, storing a result of the more significant bit compare within the translation lookaside buffer as part of an entry containing the information, and using the result of the more significant bit compare in conjunction with results from a compare of less significant bits of the information and less significant bits of compare information to determine whether a match is present. The more significant bit compare compares more significant bits of the information being loaded into the translation lookaside buffer with more significant bits of compare information.

Abstract: Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.