Abstract: The invention provides systems, devices, and methods for using more than one Accelerated Graphics Port (AGP) to process graphics for a single computer monitor (282). In one embodiment, the invention is a method of providing advanced/high-performance AGP capabilities to a laptop computer by intercepting AGP signals from a laptop having a low-power AGP (224) and converting the AGP signals to signals for a high-performance AGP (270).

Abstract: An automatic bit-rate detection scheme (30) for use in SONET/SDH transceivers (12, 14) that uses only one clocking frequency (clk), is all digital, and requires less than 250 microseconds to detect a new data bit-rate. The present invention analyzes events that are guaranteed to be present in all SONET data streams. A1 and A2 framing bytes (22,24) occur at 125 microseconds intervals in all SONET signals. The bit transitions in the framing bytes represent the minimum transition intervals of the received data. The present invention examines this bit interval to determine the operating frequency of the received data. A set of combinational logic circuits (70, 80, 90) are used to detect specific data bit patterns which appear in the A1 and A2 SONET framing bytes, such as “010” and “101”. The combinational circuit looks for specific patterns of data bits occurring at a specific communication rate.

Abstract: A low pin count (LPC) input/output (I/O) bridge device and method for a portable computer having a plurality of legacy ports and a docking connector. The LPC I/O bridge device includes an LPC controller coupled to the legacy ports and docking connector. The LPC controller is adapted to detect whether the portable computer is coupled to a docking station via the docking connector and route data transmissions to the legacy ports, docking connector, or both, based on information received from an LPC interface. Serialization logic coupled to the LPC controller serializes data transmissions routed to the docking connector.

Abstract: A low pin count (LPC) input/output (I/O) bridge device and method for a portable computer having a plurality of legacy ports and a docking connector. The LPC I/O bridge device includes an LPC controller coupled to the legacy ports and docking connector. The LPC controller is adapted to detect whether the portable computer is coupled to a docking station via the docking connector and route data transmissions to the legacy ports, docking connector, or both, based on information received from an LPC interface. Serialization logic coupled to the LPC controller serializes data transmissions routed to the docking connector.

Abstract: The invention provides systems, devices, and methods for using more than one Accelerated Graphics Port (AGP) to process graphics for a single computer monitor (282). In one embodiment, the invention is a method of providing advanced/high-performance AGP capabilities to a laptop computer by intercepting AGP signals from a laptop having a low-power AGP (224) and converting the AGP signals to signals for a high-performance AGP (270).

Abstract: A digital desynchronizer device (10) includes an elastic store unit (12) that receives data in an asynchronous manner and synchronously transmits the data in response to a synchronization clock generated by a clock generator (14). The clock generator (14) operates off of a reference oscillator unit (16). The clock generator (14) generates the synchronization clock signal in response to pointer adjustments identified by a pointer movement unit (18). The clock generator (14) also generates the synchronization clock signal in response to mapping jitter identified by a mapping unit (20). The pointer movement unit (18) and the mapping unit (20) identify pointer adjustments and mapping jitter, respectively, independent of each other. The clock generator (14) adjusts a width of a specific pulse bit in response to pointer adjustments identified by the pointer movement unit (18).

Abstract: A digital desynchronizer device (10) includes an elastic store unit (12) that receives data in an asynchronous manner and synchronously transmits the data in response to a synchronization clock generated by a clock generator (14). The clock generator (14) operates off of a reference oscillator unit (16). The clock generator (14) generates the synchronization clock signal in response to pointer adjustments identified by a pointer movement unit (18). The clock generator (14) also generates the synchronization clock signal in response to mapping jitter identified by a mapping unit (20). The pointer movement unit (18) and the mapping unit (20) identify pointer adjustments and mapping jitter, respectively, independent of each other. The clock generator (14) adjusts a width of a specific pulse bit in response to pointer adjustments identified by the pointer movement unit (18).